Problem getting LS2085ardb to work with the CodeWarrior TAP

[yanivweizman]

Hello,

We are trying to debug the reflector application over the AIOP in the LS2085aRDB (EAR5).

We followed the instructions in EAR5 documentation: "EAR5.0_AN5165_AIOP_Applications_Debug".

Code worrier TAP (cwtap) is used for debug,

Initially, when launching the debug session, we got an error: CCS last error: CC config string is invalid

Using the CCS application, we initiated the commands:

delete all

config cc cwtap

show cc

These seems to resolve the above error, however a new error related to JTAG conig_chain has been raised:

CCSProtocolPlugin : Failed to correctly configure the JTAG chain

[CCS last error: Connection refused ]

Trying to run the CCS commands did not solve the issue:

config_chain {ls2085a sap2}

ccs::reset_to_debug

CCS and JTAG debug info. within the attached file.

We are using CodeWarrior release 11.1.1 with its integrated packet processing CW_APP version 10.1.1

In addition, we are using the supplied PBL_0x2a_0x41_1333.bin PBL file from EAR5 in bank 4.

Your help is appreciated.

Best,

Yaniv.

Original Attachment has been moved to: AIOP-debug.txt.zip

[marius_grigoras]

Hi Yaniv,

Can you please let me know why are you using the RCW from bank4? Are you using the DIP SW settings for booting up from bank4? If not, you should set up the RCW and all the images to bank0.

Thank you,

Marius

[yanivweizman]

Hi Marius,

We are working with Bank4 following your EAR5.0 Quick start guide (page 149).

BTW - Also when booting from bank0, we have the same JTAG error.

Best,

Yaniv

[marius_grigoras]

Hi Yaniv,

Yes, the instructions are basically for the alternate bank (bank4) to not break the main bank (bank0) – e.g.: deleting the RCW will make impossible to u-boot again the u-boot. If you have a stable board you can continue will images and commands from bank0.

Let’s take it step-by-step:

1. 1. Setting a serial console in UART2 (second port – the top one) – reset the board – do you see any output?
2. 2. The DIP Switches are the ones bellow – can you please let me know your settings? Make sure you set up the board as bellow taking in consideration the board revision.

PCB REV B:

SW4 : 0xFF = 11111111  SW1 : 0x12 = 00010010  SW10: 0xFF = 11111111 SW3 : 0xBF = 10111111  SW7 : 0x42 = 01000010

SW9 : 0x42 = 01000010   SW6 : 0x5F = 01011111

Where '1' = DOWN/ON

PCB REV C:

SW5 : 0xFF = 11111111  SW3 : 0x12 = 00010010  SW6 : 0xFF = 11111111  SW4 : 0xBF = 10111111

SW9 : 0x42 = 01000010   SW8 : 0x5F = 01011111  SW7 : 0x42 = 01000010

Where '1' = UP/ON

1. 3. If your DIP SW settings are different comparing with the above ones, try to power off the board, enable new settings, power on, check if the u-boot is booting up and after check again the connection from ccs console
2. 4.
3. 5. Let’s debug the JTAG. Try next command from ccs console:

dele a

config cc cwtap

source IDcode.tcl

//press x because the cwtap is already configured

scanboard

There are 3 possible outputs:

1. a.       Device 0  IDCODE: 0A01E01D  Device: Unmapped FSL Device – this means the boundary scan mode is activated and is not ok – use SW5[7]=1 for setting it to DAP mode
2. b.      Device 0  IDCODE: 5BA00477  Device: Unknown Device – this is DAP mode and is OK!!!
3. c.       Worst case scenario is the bellow one and this means the JTRAG is unresponsive and should try another board L

TDO -----

|

        * Device 0  IDCODE: FFFFFFFF  Device: Unknown Device

* Device 1  IDCODE: FFFFFFFF  Device: Unknown Device

* Device 2  IDCODE: FFFFFFFF  Device: Unknown Device

* Device 3  IDCODE: FFFFFFFF  Device: Unknown Device

* Device 4  IDCODE: FFFFFFFF  Device: Unknown Device

* Device 5  IDCODE: FFFFFFFF  Device: Unknown Device

* Device 6  IDCODE: FFFFFFFF  Device: Unknown Device

* Device 7  IDCODE: FFFFFFFF  Device: Unknown Device

|

TDI -----

Thank you,

Marius

[yanivweizman]

Hi Marius,

Good news.

There was some issue in the debug configuration path toward the LS2085A-RDB_AIOP.mem file.

Once I fixed the path, it seems that debug session is starting OK.

I hope that this will close this thread.

Thanks for the tight support !!

Best,

Yaniv

[yanivweizman]

Hi Marius,

From the boot prints I see that the board revision is D: “Board: LS2085E-RDB, Board Arch: V1, Board version: D, boot from vBank: 0”

I assume it should be as Rev C.

Anyway, this is the configuration on the board (reds are the differences):

SW5 : 0xFF = 11111111  SW3 : 0x12 = 00010010  SW6 : 0xFF = 11111111  SW4 : 0xFF = 11111111

SW9 : 0x40 = 01000000   SW8 : 0x5F = 01011111  SW7 : 0x40 = 01000000

I changed the DIP SW configuration and followed your CCS commands below.

I get the following output:

Device 0  IDCODE: 5BA00477 Device: Unknown Device – this is DAP mode and is OK!!!

Now, when starting the debug session on CW, I get the following error: “Could not open memory configuration file”

Best,

Yaniv

[yipingwang]

Hello yaniv,

For this JTAG configuration problem, I add more comment, because some other customers are not aware the following configuration ether.

On LS2085RDB, DAP mode is required, the tool assume that the target board is configured for ARM debugger compliant mode, as opposed to Boundary Scan mode.

The following switches needs to be applied.

- LS2085A-RDB: SW7.7 set to ON (TBSCAN_EN_B=1)    SW7[7] = 1 - TBSCAN_EN_B is high

- LS2085A-QDS: SW5.7 set to ON (TBSCAN_EN_B=1)

Have a great day,
Yiping

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