MPC8555 Sec2.0 test using CW(Simulator ) V8.8

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MPC8555 Sec2.0 test using CW(Simulator ) V8.8

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nicholas
Contributor I

Hi there,

I plan to work on MPC8555 (e500 v1) and CDS 8555 board.

My task is to make use of inbuilt sec 2.0 engine of 8555.

Before flashing the device I wanted to simulate my code using CW simulator V 8.8 (ISS simulator )

I am not planning to use any linux interface in final board as well so doing it in firmware only

( i just want to encrypt an array of data to start with )

 

Thru the code i can access modify and set all the relevant registers of SEC2.0 engine.

I write the appropriate Descriptors as well.

However the Encrption just doesn't take place!

 

Things I do.

1. Initialize master Control Register

2. Initialize Crypto Channel 1 configuration register.

3. Write 8 dwords ( hearder and 7 descriptors for SDES in ECB mode ) in a contigious block of memory

4. Assign the Crypto Channel 1 Fetch fifo register, the address of Descriptor header.

 

According to Sec2.0 manual and the datasheet of 8555, the encryption should be initiated. 

 

Kindly guide me if I am doing any step wrong or missing something althogether.

Thanking you

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ronco
NXP Employee
NXP Employee

Hi Nicholas,

 

Your plan is excellent, except that the MPC8555 ISS simulator does not simulate the SEC.  As noted in the ISS_README.txt file in the 8.8 CodeWarrior for Power Arch installation:

 

 The instruction set simulator (ISS) is a non-cycle accurate software
model of a PowerPC Core. The model features the following:
1. MMU: virtual memory translation and permissions using TLB entries
2. Instruction and Data L1 cache: and all the L1 cache support instructions
3. Memory: simulated memory includes address range of 0x0000_0000 – 0xFFFF_FFFF
   accessible through load and store instructions.
4. Interrupts: simulates exception handling

 

The model does not support the following:
1. Cycle accuracy: the model does not have a sense of clock cycles.
   It crunches instructions in order with no cycle latencies.
2. Out of order instruction execution.
3. Microarchitectural pipeline is not modeled

 

So I'm afraid you'll have to get access to some real MPC8555 hardware before your encryption code will do anything.  The Freescale MPC8555CDS and QUICCStart_MPC8555E are two possibilities.  I hope this helps.

 

Regards,

Ron 

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ronco
NXP Employee
NXP Employee

Hi Nicholas,

 

Your plan is excellent, except that the MPC8555 ISS simulator does not simulate the SEC.  As noted in the ISS_README.txt file in the 8.8 CodeWarrior for Power Arch installation:

 

 The instruction set simulator (ISS) is a non-cycle accurate software
model of a PowerPC Core. The model features the following:
1. MMU: virtual memory translation and permissions using TLB entries
2. Instruction and Data L1 cache: and all the L1 cache support instructions
3. Memory: simulated memory includes address range of 0x0000_0000 – 0xFFFF_FFFF
   accessible through load and store instructions.
4. Interrupts: simulates exception handling

 

The model does not support the following:
1. Cycle accuracy: the model does not have a sense of clock cycles.
   It crunches instructions in order with no cycle latencies.
2. Out of order instruction execution.
3. Microarchitectural pipeline is not modeled

 

So I'm afraid you'll have to get access to some real MPC8555 hardware before your encryption code will do anything.  The Freescale MPC8555CDS and QUICCStart_MPC8555E are two possibilities.  I hope this helps.

 

Regards,

Ron 

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nicholas
Contributor I

Thanks a lot Ronco for the reply,

Yes I figured out pretty late, that ISS is actually Instruction Set Simulator:smileyvery-happy:

Once the hardware is up I will try the implementation on board itself!

Thanks again

keep up the good work

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