LS1043A DDRC init issue

[yankz]

Refer to the LS1043A-RDB board, we make our own board, the ddr4 chip is same but we can't let the bare board working.  Because without RCW we have to use HardCoded RCW and flash normal RCW to nor flash. I use the  "ARMv8\gdb\bin\aarch64-fsl-gdb.bat " and "gdb_extensions/flash/cwflash.py" tools.  but DDRC can't be initialized:

DDRC: Time out waiting for D_INIT
Memory initialization error on DDRC!
00000080

1.  Is DDRC error code 00000080 means ACE error? we calc the pcb skew params and use QCVS to change the DDR timing and write leveling, generate new python code and paste to LS1043_RDB_init.py but nothing changes.  Can you please point out something we need to check on our own hardware board or software config?

gdb.execute("monitor rcw source set 0x9F")

# print "start override RCW"

# gdb.execute("monitor rcw data set RCW1 0x08100010")

I refer to the LS1043A_RDB_init.py and want to override hardcoded RCW use "monitor rcw data set RCW1", is this correct? we tried to override MEM_PLL_RAT to 16:1 and set speed to 1600MT/s but the clock seems not change, is is possible?

3. Even If I change the rcw_src SW4 and SW5[1] to 0x9f (use hard RCW) on LS1043A RDB board and USE_SAFE_RCW=True, The Code worrior can't connect to it. I had to override RCW like this:

gdb.execute("monitor rcw source set 0x9F")

gdb.execute("monitor rcw data set RCW6 0x80004012")

Original Attachment has been moved to: LS1043A_RDB_init.py.zip

Original Attachment has been moved to: cmd.txt.zip

[yipingwang]

Hello Y Z,

I have the following suggestions for you during target board bringing up.

1. Please refer to the first section in the document Use CodeWarrior for ARMv8 to Debug U-boot and Linux Kernel and Bring up Bare Boards to do flash programming.

2. Please prepare RCW file for your target board, according to LS1043ARDB RCW provided in Linux SDK.

3. Please delete DDR initialization section in CodeWarrior initialization file, then connect CodeWarrior to the target board to program RCW to NOR flash. The flash algorithm is configured to execute in OCRAM in CodeWarrior by default.

If you counter CodeWarrior connection problem, please refer to the following to capture CCS console log to me to do more investigation.

You can do this by going to Window > Preferences > Target Connection Configuration > Logging Configuration > Logging level : Debug, Enable logging to Eclipse console.

4. Please use DDRv tool to connect to the target board to do optimization and validation.

Please refer to the document http://www.nxp.com/docs/en/user-guide/QCVS_DDR_User_Guide.pdf 

for how to use DDRv tool.

Have a great day,
TIC

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[michaelchen_nsb]

hi Yiping,

Our board is based on LS1043a, which has a different DDR with LS1043ardb. Currently, we got new DDR configure parameters which were generated by QCVS DDR Tool,.

My question is how should I integrate these codes into our code?

We are using NAND flash, and I added initialization code in function initdram() of file “board\freescale\ls1043ardb\ddr.c”, could you please help to confirm is it is correct?

[addiyi]

Once you have a configuration provided by QCVS, click on Generate Processor Expert Code and you'll find in Generated_Code folder some .c file with the ddr configuration that can be used in different application. For your case use uboot_ddr*.c file and also take a look on https://community.nxp.com/docs/DOC-330466 

Adrian