Hello leon zheng,
Please modify the following section in CodeWarrior initialization file. You could use QCVS DDRv tool to assist you to create a DDR project for your custom board and config DDR properties according to your target board, then use DDRv tool do validation to get the optimized parameters to use them to modify the following section.
def Init_DDRC():
# SDRAM_CFG
CCSR_BE_M(0x1080000 + 0x110, 0x450C000C)
# CS0_BNDS
CCSR_BE_M(0x1080000 + 0x000, 0x0000007f)
# CS0_CONFIG
CCSR_BE_M(0x1080000 + 0x080, 0x80010322)
# TIMING_CFG_0
CCSR_BE_M(0x1080000 + 0x104, 0xD0550018)
# TIMING_CFG_1
CCSR_BE_M(0x1080000 + 0x108, 0xC2C68C42)
# TIMING_CFG_2
CCSR_BE_M(0x1080000 + 0x10C, 0x0048C114)
# TIMING_CFG_3
CCSR_BE_M(0x1080000 + 0x100, 0x020C1000)
# TIMING_CFG_4
CCSR_BE_M(0x1080000 + 0x160, 0x00000002)
# TIMING_CFG_5
CCSR_BE_M(0x1080000 + 0x164, 0x04401400)
# TIMING_CFG_7
CCSR_BE_M(0x1080000 + 0x16C, 0x13300000)
# TIMING_CFG_8
CCSR_BE_M(0x1080000 + 0x250, 0x03115600)
# SDRAM_CFG_2
CCSR_BE_M(0x1080000 + 0x114, 0x00401010)
# SDRAM_MODE
CCSR_BE_M(0x1080000 + 0x118, 0x01010214)
# SDRAM_MODE_2
CCSR_BE_M(0x1080000 + 0x11C, 0x0)
# SDRAM_INTERVAL
CCSR_BE_M(0x1080000 + 0x124, 0x18600618)
# DDR_WRLVL_CNTL
CCSR_BE_M(0x1080000 + 0x174, 0x8655F606)
# DDR_WRLVL_CNTL_2
CCSR_BE_M(0x1080000 + 0x190, 0x05070600)
# DDR_WRLVL_CNTL_3
CCSR_BE_M(0x1080000 + 0x194, 0x0)
# DDR_CDR1
CCSR_BE_M(0x1080000 + 0xB28, 0x80040000)
# DDR_CDR2
CCSR_BE_M(0x1080000 + 0xB2C, 0x0000A181)
# SDRAM_CLK_CNTL
CCSR_BE_M(0x1080000 + 0x130, 0x02000000)
# DDR_ZQ_CNTL
CCSR_BE_M(0x1080000 + 0x170, 0x8A090705)
# SDRAM_MODE_9
CCSR_BE_M(0x1080000 + 0x220, 0x00000400)
# SDRAM_MODE_10
CCSR_BE_M(0x1080000 + 0x224, 0x04000000)
# CS0_CONFIG_2
CCSR_BE_M(0x1080000 + 0x0C0, 0)
# SDRAM_CFG
CCSR_BE_M(0x1080000 + 0x110, 0xC50C000C)
Thanks,
Yiping
