Flash program target memory address

[PaulWalker]

The flash programmer needs a Target Memory Address to be specified for locating its flash algorithm. This address is normally zero for locating the flash algorithm at the beginning of memory or in the small SRAM memory space or some processor. For PPC targets the exception vector (IVOR) table is normally located in the same low memory area (as per script xx_init_SRAM.tcl). How does the flash algorithm avoid overlaying with the exception vectors when specifying a Target Memory Address of zero? 

I am flash programming a NOR device connected to the IFC of a T1024 processor. I occasionally get 'core not responding' errors in the jtag log and the flash programmer fails saying 'cannot read memory address ...'. I am using a simple SRAM connection and the T1024 has 256k in CPC. I am trying to understand why I keep getting these errors. I am currently suspicious of the flash program algorithm interfering with the processor set-up and resulting in an exception or otherwise but I need further information. The error occurrence rate is about 50% of the flash programming attempts. 

Appreciate any help or pointers here.

Thanks

[June_Lu]

Please kindly follow the AN4948.

Flash Programmer for CodeWarrior Power Architecture

Thanks

[PaulWalker]

Hi, Thanks for the response. I am familiar with the flash programmer set-up process. There is nothing in the above document that answers my question. If both the flash algorithm and the PPC exception vectors are anchored at address 0, how do they not interfere with each other during programming? Thanks