Hello.
We are trying to validate our DDR4 settings on a custom LS1020A board, following the guides for the DDR Validation tool for the qoriq configuration in codewarrior. (http://cache.freescale.com/files/soft_dev_tools/doc/user_guide/QCVSDDRVGETSTARTUG.pdf )
In this guide, step 1.4, we are unable to connect to the hardware
We get a broken link next to the Target drop-down with the tooltip: Target is not ready: target does not respond and/or could not be reset.
We are using the CWTAP with USB / Ethernet connection, and we can debug programs on the system fine.
Our target settings are:
Processor: LS1020A
Probe Type: CWTAP
Target Access: CDDE
Probe Address: <mac address of CWTAP or IP Address of CWTAP or Blank>
JTAG Clock Speed: default (have tried a few different ones)
We are suspicious that this is due to the ARM not being alone on the JTAG chain, we have a Xilinx part in front of the ARM and our JTAG Config File for debugging program has:
Generic 6 1 0x3f
LS1020A <...>
DAP
SAP2
Any ideas?
Solved! Go to Solution.
Because in this moment QCVS tool doesn't provide an option for customize the jtag chain and changing the test script could be used as workaround. For this go to eclipse\Optimization\resources\QorIQ\common\templates\init\ and edit:
connect.py, connect_to_target function:
cpuVariant = [ [6, 1, 0x3F], "LS1021A" ]
connect_call.py:
cpuVariant = [ [6, 1, 0x3F], "LS1021A" ]
After that, restart CW/eclipse.
Adrian
Because in this moment QCVS tool doesn't provide an option for customize the jtag chain and changing the test script could be used as workaround. For this go to eclipse\Optimization\resources\QorIQ\common\templates\init\ and edit:
connect.py, connect_to_target function:
cpuVariant = [ [6, 1, 0x3F], "LS1021A" ]
connect_call.py:
cpuVariant = [ [6, 1, 0x3F], "LS1021A" ]
After that, restart CW/eclipse.
Adrian
Thanks for your reply, Adrian.
I changed the file /opt/Freescale/CW4NET_v2016.01/Common/QCVS/Optimization/resources/QorIQ/common/templates/init/connect.py and /opt/Freescale/CW4NET_v2016.01/Common/QCVS/Optimization/resources/QorIQ/common/templates/init/connect_call.py to include the changes as listed below. however, i see this in CCS.
CCS output |
---|
loading history file ... 48 events added CodeWarrior Connection Server console display active (Tcl8.4.6 / Tk8.4.6) Loading CCSAPI Tcl interface (/opt/Freescale/CW4NET_v2016.01/Common/QCVS/Optimization/target-connection/cdde/ccs/bin/ccstcl.so)... Loading Svfburner (/opt/Freescale/CW4NET_v2016.01/Common/QCVS/Optimization/target-connection/cdde/ccs/bin/svfburner.so)... CC config string is invalid Server listening on port: 41475 Server listening on port: 50000 Clients allowed from all hosts No clients denied CCSAPI connection #1 accepted from localhost at Tue May 31 08:31:05 2016 CCSAPI connection #1 from localhost closed at Tue May 31 08:32:25 2016 |
And the connection fails. I have three connections in codewarrior, one with the CWTAP id left blank (should use USB), one with the MAC address of the device, and one with the IP address of the device. Each one will report "Connection script timed-out! Please verify that the target and target probe are connected and configured correctly."
connect.py |
---|
... tcf.show_info(False) # Workaround for our JTAG chain, which has a Xilinx part on it cpuVariant = [ [6, 1, 0x3F], "LS1021A" ] # Workaround for LS102x connectivity, that needs a special target name format. Example: [['LS1020', 'Rev1']] instead # of 'LS1020'. if cpuVariant in armv7_devices and majorRev == 1: cpuVariant = [[cpuVariant, 'Rev1']] ccsPort = int(get_cmdline_argument(CCS_PORT_SHORT_ARG, CCS_PORT_LONG_ARG)) ... |
I'm wondering about the snippet about 'Rev1', if it will have impact on this situation here ... Our silicon is rev 2.0 iirc.
I tried with the workaround before and after the if block
connect_call.py |
---|
# Connect to CDDE cddeConn = cdde.connect() # Create a protocol instance and save it p = cddeConn.p # variables set from the software calling this script cpuVariant = "<<{CPU_VARIANT}>>" majorRev = <<{CPU_MAJOR_REV}>> probeId = "<<{TAP_ID}>>" jtagSpeed = <<{JTAG_SPEED}>> checkBasicTargetOps = <<{CHECK_BASIC_TARGET_OPS}>> # Workaround for our JTAG chain, which has a Xilinx part on it cpuVariant = [ [6, 1, 0x3F], "LS1021A" ] # Connect to target (conn, succeeded, reseted) = connect_to_target(p, cpuVariant, majorRev, probeId, jtagSpeed, checkBasicTargetOps, False) if not succeeded: exit(-1) |
Any ideas?
Could you send a verbose log from ccs console (log v), when QCVS is trying to connect to the board?
Adrian
CCSAPI connection #1 accepted from localhost at Wed Jun 1 10:50:13 2016
check_min_version(serverh=0,*version)
api version: 00000004 00000006
available_connections(serverh=0,*count,*cc)
connections: {0,73,0xa9feeefb}
cc_version(serverh=0,cc_index=0,index=1912679227,*version)
config_chain(serverh=0,cc=0,count=4,*devlist,*generic)
devlist: unknown(0),ls1020a,dap,sap2
reset_to_debug(serverh=0,cc=0)
ERROR(39): Subcore error encountered during multicore operation
parse_error_ext(coreh.{serverh=0,cc_index=0,chain_pos=0}, 39)
error: LS1020A: Core not responding
CCSAPI connection #1 from localhost closed at Wed Jun 1 10:50:16 2016