Using the MC56F83000x EVK with CodeWarrior IDE. I have written simple program to invoke an ISR from PIT_0 timeout. I used Graphical Configuration Tool (GCT) to set up PIT_0 registers for priority, timeout and ISR linkage. But the ISR is never invoked I assume because the pitCntr is never incremented. I can't see what is missing. I could gratefully use some help. The main() and appconfig.h are shown.
main.c
#include "qs.h"
#include "sys.h"
#include "intc.h"
#include "gpio.h"
#include "cop.h"
#include "pit.h"
/* board-specific LEDs and buttons */
#include "../board.h"
void PIT0_ISR(void);
static int pit0Cntr = 0;
void main(void)
{
UWord16 i;
/* initialize SYS, COP and pins */
ioctl(SYS, SYS_INIT, NULL);
ioctl(COP, COP_INIT, NULL);
// Initialize PIT
ioctl( PIT_0, PIT_INIT, NULL );
ioctl(GPIO_LED_R2, GPIO_SETAS_GPIO, LED_B2);
ioctl(GPIO_LED_R2, GPIO_SETAS_OUTPUT, LED_B2);
ioctl(GPIO_LED_R2, GPIO_SET_PIN, LED_B2);
/* configure Interrupt Controller */
ioctl(INTC, INTC_INIT, NULL);
/* enable interrupts in SR */
archEnableInt();
ioctl( PIT_0, PIT_COUNTER, PIT_ENABLE );
while(1)
{
/* wait a while */
for(i=0; i<100; i++)
archDelay(0xffff);
/* toggle green LED indicator */
ioctl(GPIO_LED_B2, GPIO_TOGGLE_PIN, LED_B2);
/* service COP watchdog (if enabled) */
ioctl(COP, COP_CLEAR_COUNTER, NULL);
}
}
#pragma interrupt on
void PIT0_ISR(void)
{
ioctl( PIT_0, PIT_CLEAR_ROLLOVER_INT, NULL );
pit0Cntr++;
}
#pragma interrupt off
/*******************************************************************************
*
* File Name: appconfig.h
*
* Description: file for static configuration of the application
* (initial values, interrupt vectors)
*
*****************************************************************************/
#ifndef __APPCONFIG_H
#define __APPCONFIG_H
/*.*************************************************************************
*
* File generated by Graphical Configuration Tool Sun, 11/Sep/2022, 22:22:47
*
****************************************************************************.*/
#define MC56F83789
#define EXTCLK 8000000L
#define EXTAL 8000000L
#define APPCFG_DFLTS_OMITTED 1
#define APPCFG_GCT_VERSION 0x0207000dL
/*.
OCCS Configuration
--------------------------------------------
Enable internal 200 kHz oscillator: No
Power Down crystal oscillator: No
Core frequency: 50 MHz
VCO frequency: 200 MHz
Loss of lock interrupt 0: Disable
Loss of lock interrupt 1: Disable
Loss of reference clock Interrupt: Disable
.*/
#define OCCS_CTRL_INIT 0x0085U
#define OCCS_DIVBY_INIT 0x2018U
#define OCCS_OSCTL1_INIT 0x0220U
#define OCCS_OSCTL2_INIT 0x8100U
/*.
SYS Configuration
--------------------------------------------
SIM: Power Saving Modes: Stop enabled
Wait enabled
OnCE clock to processor core: Enabled when core TAP enabled
DMA Enable in RUN and WAIT modes: DMA enabled in all power modes
Enable External Reset Input Filter : No , SIM - Clock on GPIO: Enable CLKO_0: No
SIM - Clock on GPIO: Enable CLKO_1: No
SIM - Peripheral Clock Enable: GPIO G: No , GPIO F: Yes, GPIO E: Yes, GPIO Yes, GPIO C: Yes, GPIO B: No , GPIO A: No , TMR A0: No
TMR A1: No , TMR A2: No , TMR A3: No , TMR B0: No , TMR B1: No , TMR B2: No , TMR B3: No , DAC_A: No
DAC_B: No
SCI_0: No , SCI_1: No , SCI_2: No , QSPI_0: No , QSPI_1: No , IIC_0: No , IIC_1: No , FLEXCAN: No
CMP A: No , CMP B: No , CMP C: No , CMP No , CYC ADC: No , CRC: No , PIT_0: No , PIT_1: No , PWMA_SM0: No , PWMA_SM1: No , PWMA_SM2: No , PWMA_SM3: No
PWMB_SM0: No , PWMB_SM1: No , PWMB_SM2: No , PWMB_SM3: No , ROM: No , SIM - Modules Enabled in Stop: GPIO G: No
SIM - Modules Enabled in Stop: GPIO F: No , GPIO E: No , GPIO No , GPIO C: No , GPIO B: No , GPIO A: No
TMR A0: No , TMR A1: No , TMR A2: No , TMR A3: No , TMR B0: No , TMR B1: No , TMR B2: No , TMR B3: No , DAC_A: No
DAC_B: No
SCI_0: No , SCI_1: No , SCI_2: No , QSPI_0: No , QSPI_1: No , IIC_0: No , IIC_1: No , FLEXCAN: No
CMP A: No , CMP B: No , CMP C: No , CMP No , CYC ADC: No , CRC: No , PIT_0: No , PIT_1: No , PWMA_SM0: No , PWMA_SM1: No , PWMA_SM2: No , PWMA_SM3: No
PWMB_SM0: No , PWMB_SM1: No , PWMB_SM2: No , PWMBSM3: No
ROM: No , USB: No , Protection of IPS and GPSxx : Registers not protected
Protection of PCE, SD and PCR: Registers not protected
Protection of GPIO Port Registers not protected
Protection of PWRMODE: Registers not protected
GPIO Peripheral select registers (GPSn): ANA0/CMPA3
USB_SOFOUT
ANB1/CMPB_IN0
CMPD_O
EXTAL
XB_IN2
TA0
TA1
XB_IN7
TA2
SS0_B
MISO0
SCLK0
MOSI0
CANTX
CANRX
TA3
SDA0
SCL0
RXD2
TXD2
XB_OUT11
PWMA_0B
PWMA_0A
PWMA_1B
PWMA_1A
PWMA_2B
PWMA_2A
PWMA_3B
PWMA_3A
PWMB_2B
PWMB_2A
XB_IN6
CLKO_1
MISO1
SDA1
PWMA_FAULT6
RXD1
PWMA_3X
SS1_B
RXD0
XB_OUT11
XB_OUT10
TXD0
MISO1
MOSI1
SCLK1
RXD0
PWM1B
PWM1A
PWM0B
PWM0A
PWM3B
PWM3A
PWMA_FAULT4
PWMA_FAULT5
PWMB_0X
PWMB_1X
PWMB_2X
TB3
Internal Peripheral Select Register 0 (IPS0): GPIO C3
GPIO C4
GPIO C6/G8
GPIO C13/G9
GPIO C2
GPIO F8
GPIO F6/F0/G6
GPIO F7/G11
FAULT0 input pin (GPIO E8)
FAULT1 input pin (GPIO E9)
FAULT2 input pin (GPIO G4)
FAULT3 input pin (GPIO G5)
FAULT0 input pin (GPIO F14)
FAULT1 input pin (GPIO F13)
FAULT2 input pin (GPIO F12)
Miscellaneous Register 0 (SIM_MISC0): CLKIN0 (GPIOC0 alt1)
PIT1 master, PIT0 slave
Normal Order
Enable
SIM - Interrupts: Low voltage 2.2V: Disable
Low voltage 2.7V: Disable
High voltage 2.2V: Disable
High voltage 2.7V: Disable
Enable Voltage Reference Buffer: No
Bandgap trim: 7, Use Factory Trim Value: No
Power Control: Large Regulator Standby mode: Normal
Small Regulator 2.7 V Supply Standby mode: Normal
Small Regulator 2.7 V Supply Powerdown mode: Normal
Small Regulator 1.2 V Supply Standby mode: Normal
Xbar Input from ADC and TMRA/B (SIM_ADC_TMR_SEL): TMRB0
TMRB1
TMRB2
TMRB3
TMRA0
TMRA1
TMRA2
TMRA3
Xbar Input from PWMA and PWMB (SIM_PWM_SEL): PWMA0 Mux Trig0
PWMA0 Mux Trig1
PWMA1 Mux Trig0
PWMA1 Mux Trig1
PWMA2 Mux Trig0
PWMA2 Mux Trig1
PWMA3 Mux Trig0
PWMA3 Mux Trig1
PWMA0 Out Trig0
PWMB0 Mux Trig1
PWMB1 Mux Trig0
PWMB1 Mux Trig1
PWMB2 Mux Trig0
PWMB2 Mux Trig0
PWMB3 Mux Trig0
PWMB3 Mux Trig1
Change boot flag bits (SIM_BOOT_MODE_OVERRIDE): FOPT[6,7] not masked
.*/
#define SIM_CLKOSR_INIT 0xD020U
#define SIM_GPSAH_INIT 0x00C0U
#define SIM_GPSCL_INIT 0x0420U
#define SIM_GPSFL_INIT 0x9320U
#define SIM_GPSFH_INIT 0x003CU
#define SIM_PCE0_INIT 0x001EU
#define SIM_PCE1_INIT 0x0002U
#define SIM_PCE2_INIT 0x0000U
#define SIM_PCE3_INIT 0x0000U
#define SIM_MISC0_INIT 0x0041U
#define SIM_PWM_SEL_INIT 0x0100U
/*.
INTC Configuration
--------------------------------------------
.*/
#define INTC_ICTL_INIT 0x0000U
#define INT_VECTOR_ADDR_95 PIT0_ISR
#define INT_PRIORITY_LEVEL_95 INTC_LEVEL0
/*.
PIT_0 Configuration
--------------------------------------------
Counter Enable: Enable
Clock Prescaler: / 32768
Modulo Value: 18
Interrupt Enable: Enable
Clock source: IPBus clock
.*/
#define PIT_0_CTRL_INIT 0x007BU
#define PIT_0_MOD_INIT 0x0012U
/*. End of autogenerated code
********************************************************************** ..*/
#endif
