Hi All,
I wonder if anyone else has seen the problems I have suddenly started to encounter and has any solutions?
I have been running Metrowerks debugger with a P&E BDM pod (Parallel not USB) on the HCS12A512 for over a year now and this is the first time I have seen this, which is suspicious in itself!!
I start my project, which does some initial checks and enters normal run mode - it seems to run like this for around 1 - 5minutes. During this time I can check internal memory, breakpoint etc as you would expect and all looks normal...
But then, I encounter an illegal breakpoint at the Clock Monitor Fail Vector, All the registers - PC, IP, D, A, B, IX, IY are populated with FFFF - which I think is consistent with the chip coming out of reset - although wierdly, having checked all the docs, I have disabled the clock monitor fail interrupt!?
But, I have written debug software so I can interrogate the chip status through the SCI - and with the debugger showing the chip halted, I can still send and receive debug messages. Further - these messages indicate that the chip has not been reset, as internal message counters have not been cleared!!
So, it seems that the metrowerks debugger has gotten confused somehow, indicating the chip has crashed when it has not - I have read other posts that indicate running the debugger with PLL enabled can cause problems, and my project does use the PLL module, ramping the source 25Mhz crsytal up to 50Mhz. However, I have run my project for at least 6 months with these PLL settings without apparent problems.
Has anyone else seen wierd effects like these, or have any workarounds?
Thanks in advance,
Mike
