'waiting for hw sem' loop

[chandramills]

I have been working on some ipc examples to demonstrate data flow between DSPs and PPC on the B4860 eval board. The examples worked with data transferring between the PPC and StarCore. Then I started working on the ipc_integration example provided by Freescale to give our team a more simple example to work from, but a little while after I started, the hardware semaphore that syncs the PPC and StarCore to allow messages to be sent and received no longer worked: I just got "sleep 1, waiting for hw sem", repeated (while using /ipc/dsp_bt to load the DSPs with the binaries compiled by CodeWarrior). I also tried to revert to my old examples, which previously worked, and they had the same response. IPC just stopped working. I then looked to CodeWarrior to see what was happening, and when I entered the Debug configuration, the instruction pointer was at 0x0, and I could only see DEAD BEEF in memory. Any thoughts as to why this is happening and what I can do about it?

[lana0]

Hi everyone!

I need to establish an IPC layer for our project on B4860QDS and eventually

Like to start from some working example!

I've found the LINUX (PA) side example sources in ipc-ust folder in git distribution.

But I fail to find any sources for SC DSP side?? Which are mandatory for IPC test.

The release pdf suggests as example to run the sequence

 ./dsp_bt -h 1 -c 0 -i c0.bin -c 1 -i c1.bin

But the source of these bins never mentioned in pdf . It is pure magic that lot of people in this forum succeeded to run it!

It is nice to get bin files here, but sources preferable.

Please help. I am using SC CodeWarrior 10.3

I've browsed the toolchain for SC compiler and found some files for ipc but they have no the same control structures as release 2.0 for LINUX SDK for PA.

On PA side, it is also make include for  fsl_bsc913x_ipc.h. Should it be used for b4860QDS also?

Thank in advance.

[yipingwang]

Hello Chandra Mills,

According to your description, it seems that DSP side doesn't boot up correctly. Probably the problem is related with ipc tool or DSP boot code. Please refer to the following procedure to setup IPC channel to load DSP boot code.

System configuration to build images:

1. Disable the Kernel dma engine Device Drivers  --->  [ ] DMA Engine support  ---> 2. Enable Userspace's I/O driver Device Drivers  --->  <*> Userspace I/O drivers  --->   <*> Freescale DMA support 3. Build below packages into rootfs NOTE: meta-fsl-networking/images/fsl-image-core.bb IMAGE_INSTALL += " \     ipc-ust \     ipc-modules-single \     ipc-modules-multi \ "

Actions on the target board.

1. Append bootargs with 'default_hugepagesz=256m hugepagesz=256m hugepages=1'    2. Add  new environemnet varible by => setenv bootm_size 0x70000000 3. Insmod required kernel moduls: # insmod /usr/driver/IPC/single_rat/hetmgr.ko # insmod /usr/driver/IPC/single_rat/shm.ko # insmod /usr/driver/IPC/single_rat/l1d.ko 4. Create device nodes for above kernel modules: # mknod /dev/het_mgr c 251 0 # mknod /dev/fsl_shm c 250 0 # mknod /dev/fsl_l1d c 249 0 5. Set shmmax value: # echo 0x10000000 > /proc/sys/kernel/shmmax 6. Copy DSP binaries to board: 7. Load SDOS images to DSP cores: # ./dsp_bt -h 1 -c 0 -i c0.bin -c 1 -i c1.bin 8. Start ipc: # ./ipc_test -r 0 -i 10 (10) Msg Sent on ch#5 (10) Msg Recieved on ch#4 (10) Msg Sent on ch#2 (10) Msg Recieved on ch#3 Success on ch#2-ch#3 pair Success on ch#4-ch#5 pair root@b4860qds:/ipc# Thanks, Yiping

[chandramills]

Thanks for your reply.

Is there any guide to converting code from version 10.8.3 to 10.9?