T1040d4 custom board without CPLD, JTAG programming issue

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

T1040d4 custom board without CPLD, JTAG programming issue

跳至解决方案
2,044 次查看
Wj_khi
Contributor II
Hi I have custom board designed using T1040d4 qoriq powerpc. My bareboard powerpc is currently power on using onboard power sequencing without using any CPLD. Right now i have no serial interface to monitor and debug it as both T1040 UART interfaced are attached with some other hardware over custom board. #Issue# when attached via CW usb tap its Jtag unable to program and flash bootloader via code warrior it shows " IR scan measure error" also "core not responding " in jtag log console.
标记 (1)
0 项奖励
回复
1 解答
2,038 次查看
yipingwang
NXP TechSupport
NXP TechSupport

Please check whether your JTAG interface hardware design is similar as the following

yipingwang_0-1616749172774.png

If the test fails to measure the length of the instruction register, then an error, Error measuring IR length, is thrown.
The error might be due to one or more of the following reasons:
• TRST stuck low: This may hold the target JTAG logic in reset, preventing any shifts to occur.
• TMS disconnected or stuck: This may prevent the target from making any JTAG state changes.
• TCK disconnected or stuck: This may prevent any state changes or clocking of data.
• TDI disconnected or stuck: This may prevent the test pattern data from getting into the target.
• TDO disconnected or stuck: This may prevent the test pattern data from getting out of the target.
If the test fails, then it is possible that there is a physical connection problem with the JTAG pins, or the JTAG frequency is too high.

 

 

在原帖中查看解决方案

0 项奖励
回复
2 回复数
2,039 次查看
yipingwang
NXP TechSupport
NXP TechSupport

Please check whether your JTAG interface hardware design is similar as the following

yipingwang_0-1616749172774.png

If the test fails to measure the length of the instruction register, then an error, Error measuring IR length, is thrown.
The error might be due to one or more of the following reasons:
• TRST stuck low: This may hold the target JTAG logic in reset, preventing any shifts to occur.
• TMS disconnected or stuck: This may prevent the target from making any JTAG state changes.
• TCK disconnected or stuck: This may prevent any state changes or clocking of data.
• TDI disconnected or stuck: This may prevent the test pattern data from getting into the target.
• TDO disconnected or stuck: This may prevent the test pattern data from getting out of the target.
If the test fails, then it is possible that there is a physical connection problem with the JTAG pins, or the JTAG frequency is too high.

 

 

0 项奖励
回复
2,030 次查看
Wj_khi
Contributor II

Thanks for reply. TDI and TMS signals are pulled up with 10k resisters. This difference  i observed in your shared jtag logic schematic and with my followed t1040d4rdb "COP Connector " schematic section. Is there any effect of it regarding my jtag issue.

0 项奖励
回复