QCVS DDR margin tool

[OneNote]

Hi

In our latest codewarriro QCVS, the margin page of DDR validation doesn't have Margin stage as scenarios, only has Diags margin stage. Why this happen? What's the cause?

Thanks.

[yipingwang]

What processor are you using now?

Which version QCVS tool are you using?

[OneNote-0]

Thanks, Yiping.

Processor: LX2160A

QCVS version: 4.23

[yipingwang]

Margin stage is removed since QCVS 4.23 2020.11 release.

Margin stage scenario is no longer available for LX2, but is should be available for the rest of devices.

If further information is needed, please feel free to let me know.

[OneNote-0]

Thanks.

Further question: how to test margin? use diag margin stage?

[yipingwang]

I just got confirmation from the development team.

Yes, you should use the diag margin stage.

[OneNote]

Thanks.

Now it's back to 4.22.

There is a new issue happen when run the margin test.

Log attached.

[yipingwang]

Please open CCS console on the right bottom of your task bar, type "log v", then connect to the target board again, the low level CCS log will be printed out.

Please send the CCS console log to me to do more investigation.

[OneNote]

Is this what you want? Thanks.

[OneNote]

[yipingwang]

It failed at "reset_to_debug". If the RCW is valid, probably there is hardware design problem of the JTAG interface on your custom board.

[OneNote]

Measured the reset signals, when nRESET is low, PORESET_B also is low. And also found the HRESET_B is low and keep low always.Is it a clue?

[yipingwang]

Would you please refer to "3.2 Working with bareboard application" in the attached document to create a board board project and run it on your target board.

Please click "Target Connections->LX2160A_RDB(1)->Edit->Target Initialization File", 

please modify "USE_SAFE_RCW = False" to "USE_SAFE_RCW = True".

Then connect to the target board, and send CCS console log to me, I just want to check whether the core can be stopped.

[OneNote]

[yipingwang]

Please modify "USE_SAFE_RCW = False" to "USE_SAFE_RCW = True" in CW initialization file and save the configuration.

[yipingwang]

Please also try the following commands in CCS console.

delete all

config cc cwtap:<ip>

ccs::config_chain {lx2160a dap}

display ::ccs::get_config_chain

::ccs::stop_multi_core {21}

::ccs::reset_to_debug

[OneNote]

[yipingwang]

Please try to run a bareboard application with hard-coded RCW as I mentioned in my previous post.

[OneNote]

[yipingwang]

As I mentioned previously, please modify "USE_SAFE_RCW = False" to "USE_SAFE_RCW = True" in CW initialization file and save the configuration, then run the bareboard application.

[yipingwang]

Is it possible to provide your JTAG design schematics for the custom board?