DDR validition D_INIT

[matthewboutin]

P1011 DDR3 clock centering validation fails with D_INIT. Some cells pass, some fail. We turn EEC on and we get more failures. Should we leave ECC off to run this test. Also READ ODT and WRITE ODT all fail with D_INIT when we use the WRLVL and CLK adjust settings when ECC was on. If we use the clock centering values we obtained with ECC off READ ODT and WRITE ODT passes some values. Signal integrity looks good.

[yipingwang]

Hello Matthew Boutin,

Please check DDR controller configuration in CW initialization file, whether these two bits DDR_SDRAM_CFG[ECC_ON]  and DDR_SDRAM_CFG_2[D_INIT]  are set when ECC is on.

Have a great day,
Yiping

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[matthewboutin]

Hello Yiping,

Thank You for the reply. The settings above were correct during our testing. We found that DDR_Reset was not toggling when the JTAG POD HRESET was toggling which gave us bad results. This is an undocumented requirement for the tool. After connecting HRESET to DDR_Reset our results were good.  It would be good to have this requirement documented in an application note or specification for the memory validation tool.

Thank You for your reply

mb