Hello Mike,
I am not familiar with your board, but I believe that communications between the MCU and the 13192 uses the SPI, with the MCU as the master. So the MCU has control over all SPI operations. What is the specific interrupt used for these communications? Is the ISR processing likely to take more than 80 microseconds? If so, this would be a very long ISR.
Another issue could be the presence of timer interrupts, since these have higher priority than the SCI interrupt for the serial port. Could there be any reason for an associated ISR processing to be prolonged?
Can I presume that the existing ISR for the SCI receive interrupt simply clears the interrupt flag, reads the incoming character value, places it in a FIFO buffer, and then exits? This assumes that the processing of the contents of the receive buffer would occur outside of any ISR.
Since the read and storage of an incoming serial character should be a quick process, there is probably no reason the same thing can't be done at the beginning of other ISRs in the event that the RDRF flag for the SCI is set. This should prevent the possibility of over-run errors due to the ISR processing time, and without the complexity of re-enabling interrupts within an ISR. In the event of a very lengthy ISR (not sure why this would be so) you mignt need to test the RDRF flag more than once throughout the ISR.
Still not sure about your compile problem - I would need more information than the big long comment of your last post - perhaps the actual C code of the ISR of concern.
Regards,
Mac