XCLK on QG4/8

[billw]

Ok, I read the datasheet, I looked at AN3041, and even some of the code
exmaples, but I'm still confused.
XCLK is the "fixed frequency clock" selectable as inputs to the timers,
and is apparently typically lower in frequency than the bus clock. But
where does it come from and what's its value on these chips with fancy
clock circuitry? Is it the same as the internal reference clock (~32kHz?)
Is it a divided version of the bus clock? The only docs for the source of
xclk was figure 1-2 in the datasheet, and i didn't find it helpful. All
other mentions of xclk describe how it is selected as an input for the
assorted timers and such.

Thanks
Bill W

[bigmac]

Hello Bill,

According to figure 1-2 in the datasheet, XCLK may be derived from either ICSFFCLK divided by 2, or alternatively from the bus clock, depending on the state of the ICSFFE control bit.

Then from figure 10-2, ICSFFCLK is derived from either the internal reference clock or an external reference, but will always be within the limits 31.25 to 39.0625 kHz.  Therefore, I would expect XCLK to be one half this frequency when ICSFFCLK is selected as the source.

Regards,

Mac

[bigmac]

Hello again,

To slightly clarify my previous post, after some further reading -

The ICSFFE signal is automatically enabled provided the frequency of ICSOUT exceeds the frequency of ICSFFCLK by a factor of four, or greater (i.e. the bus frequency is at least four times the XCLK frequency).  The reason for this restriction is not clear to me.  Paragraph 10.4.7 of the datasheet explains the special conditions for which ICSFFE would be disabled.  But otherwise, what I stated in my previous post would seem to apply.

Regards,

Mac

[billw]

So xclk will usually be irc/2 (~16kHz), unless the clock generator
is configured for particularly low frequencies, in which
case it would be the same as the bus clock.

Ok, thanks.
BillW