Timing spec source for "want min 4~ from w cycle to r"?

[ElfShottheFood]

In various Freescale assembly language bootloader and flash programming files (i.e. doonstack.asm), there's a NOP instruction in the SpSub routine between writing and reading FSTAT.  The comment on that line is "want min 4~ from w cycle to r".

I understand the need for a delay, but where does the number 4 come from, as in which spec?  Does the 4 refer to Fclks, microseconds, something else?  So far I haven't had any luck locating the actual required time between writing and reading FSTAT.  I'm using a QE128, and I couldn't find any relevant info in there about this (just a reference to typical flash program time of 4 Fclks).

Thanks!

[ElfShottheFood]

Excellent!  Thanks for the great response, peg.  Everything makes sense now.

[peg]

Hello and welcome to the fora.

The 4 cycles referred to here is CPU clock cycles.

The access details for an Extended mode STA is pwpp

and for an extended mode LDA is prpp.

Thus if you do a LDA then STA there will be 3 cycles between the w (write) and the r (read).

The NOP added between extends this to 4 cycles as this is the time required "so the internal FLASH command sequencer can properly update the FCBEF and FCCF flags in FSTAT".

This timing is independent of the flash clock.

The details of the FLASH operation are all a bit of a secret, possibly due to the fact that the technology is only licensed by freescale.

[bigmac]

Hello,

In practice, rather than using a single NOP instruction, I might suggest implementing a COP timer reset within the wait loop.  This will avoid any possibility for COP reset to occur during the sector erase process, and will then easily meet the internal timing requirements.

Regards,

Mac