Hello Andrea,
The problem is your ClrData macro! Making some substitutions to clarify the operation, the macro becomes as follows -
#define ClrData PTBD_PTBD3 = 0; PTBDD_PTBDD3 = 1
If the MTIM interrupt should occur after the first part of the macro has completed, but prior to the second part, the PTBD3 state will revert to a 1, for the reason previously mentioned. This problem should be eliminated with either of the following variations -
#define ClrData __asm sei; PTBD_PTBD3 = 0; PTBDD_PTBDD3 = 1; __asm cli
This is equivalent to Tony P's xuggestion, and will prevent the interrupt from occurring at the critical point.
#define ClrData PTBDD_PTBDD3 = 1; PTBD_PTBD3 = 0
This may actively drive the pin high for a few cycles before the port pin is set low, but may be acceptable for the IIC case, provided the slave device is not driving low at this point.
You should also handle the SCL pin in a similar manner for the clock low state.
Regards,
Mac