Relationship between ICG Filter Register and BusClock in SCM Mode

[Denn]

Hello All,

Do anyone know the relationship between the ICG Filter Registers (ICGFLTU, ICGFLTL) value and the BusClock / DCO output freq  in SCM Mode.

I know that the default value of 0x00C0 will yield fICGOUT of 8MHz and BusClk of 4MHz.

Also BusClk= 0.5( fICGOUT) = 0.5( fICGDCLK/ R )

where R = Division Factor(R). Page 141 HCS908AWdatasheet

Datasheet states that "The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value into the filter registers (ICGFLTH and ICGFLTL)."

Now I want to set ICG Filter Registers (ICGFLTU, ICGFLTL) such that Busclk should be 8MHz.No where can I see the info relating to this filter register and DCO output freq.

Also refer the link of the post.

http://forums.freescale.com/freescale/board/message?board.id=8BITCOMM&message.id=8878&query.id=19836...http://forums.freescale.com/freescale/board/message?oard.id=8BITCOMM&message.id=8878&query.id=19836#...

Regards,

Denn.

[Denn]

Hello All,

The value of ICGFLT Filter is varying from part to part. Can anyone explain why its so.It was supposed to be constant.

In SCM mode the clock source used is 8MHz internal oscillator. Filter register comes into picture(DON"T KNOW HOW)

ICGOUT= 8MHz/R=8MHz/1 (POR value of R=1) and hence Bus Clk= ICGOUT(0.5)= 4 MHz.

Can anyone speculate whats happening in filter register and how

-Denn.

[fabio]

Hi Denn,

When you say: "The value of ICGFLT Filter is varying from part to part", you mean that when you set the ICG to FEI mode, the ICGFLT register is being set (by hardware) with different values (for the same MFD factor), from one device to another?

I did not understand why you trying to rise the SCM speed in early initialization. Could you explain us what are your needs?

One possible solution I can figure out right now is the following:

1- During initialization, the application looks for a non 0xFF value in an specific address.
2- If the value is 0xFF, the application proceeds with standard init (running at 4MHz BUSCLK) and later changing to FEI mode.
3- Once FEI mode is stable (FLL locked), the application stores the ICGFLT values onto FLASH.

On the next initialization, the init procedure will find these values in FLASH and configure the ICGFLT accordingly. This way, only the first init will leave the ICG at 4MHz, all others will work at 8MHz (or whatever speed you choose). Just remember that while the ICGIRCLK is untrimmed, it can lead the ICGOUT to be out of specs!

Hope it helps!

[bigmac]

Hello Denn,

Keep in mind that, if you are programming in C, any code that increases the SCM frequency will not be executed until after the ANSI initialisation of variables is completed.  This code will therefore be executed using the approximate 4 MHz bus frequency.  So there would seem little point in making the filter adjustment - perhaps just immediately implement FEI mode at the beginning of main().

Regards,

Mac

[fabio]

I agree with you Mac,

The only concern may be the FLL synchronization time that can be as long as 5ms.

Regarding the C language, it is always possible to modify the assembly startup code to include the filter adjustment instructions...

But Denn, is your application so critical that you can't wait until FEI mode is fully engaged?

Regards,

[bigmac]

Hello Fabio,

Are you aware of any evidence to suggest that, by setting the SCM frequency to be in the vicinity of the eventual FEI mode frequency, whether this would result in a significantly shorter synchronization time for FEI?

If so, this might be justification for storing the required filter value as a non-volatile parameter.  However, I would guess that the calibration value may be quite temperature and Vdd dependent.

Modification of the C startup code I would consider to be a last resort, and not to be undertaken lightly.

Regards,

Mac

[fabio]

Hi Mac,

---

bigmac wrote:

Hello Fabio,

Are you aware of any evidence to suggest that, by setting the SCM frequency to be in the vicinity of the eventual FEI mode frequency, whether this would result in a significantly shorter synchronization time for FEI?

---

No, what I wanted to say is that it is possible to set the filter registers early in the startup code. I don't really know if presetting the filter register will cause a faster FLL synchronization. That is a good question indeed.

Again, I agree with you that selecting FEI mode in the beginning of the main() would probably work ok, unless Denn's application is so critical it can't stand for the necessary time for FLL synchronization.

Regards,

[Denn]

Hello Fabio,

"When you say: "The value of ICGFLT Filter is varying from part to part", you mean that when you set the ICG to FEI mode, the ICGFLT register is being set (by hardware) with different values (for the same MFD factor), from one device to another? "

Yes you got it right.By going to FEI mode, I read the contents of ICGFLT register so that I can use this in startup code.But this value is changing from one MCU to another MCU unit (All AW32 MCUs)

"I did not understand why you trying to rise the SCM speed in early initialization. Could you explain us what are your needs?"

I'm trying this because if there comes a situation(sometimes it happens in the lifetime of a product) where during the normal operations, the FEI FLL loses lock then DCO output is open looped and (as a fail safe method ) it has to be close to my normal 8MHz Bus CLK. Reason for going this fail safe method is LIN commn protocol fails if its away from 9600 baud +/-2% (clock for LIN is derived from Bus Clk)

I can go for LOSS OF CLOCK reset feature.But if I see from the product/system point of view, also End user point of view I shouldnot (or should avoid) resets(sudden abrupt in normal working of the product)

"On the next initialization, the init procedure will find these values in FLASH and configure the ICGFLT accordingly. This way, only the first init will leave the ICG at 4MHz, all others will work at 8MHz (or whatever speed you choose). Just remember that while the ICGIRCLK is untrimmed, it can lead the ICGOUT to be out of specs!
"

I was thinking of doing this.Read from flash and load in filter register in the assembly startup.

Yes you are right. My ICG internal oscillator has a trimming routine and I saw the perfect busclock of 8MHz(through MCLK pin=busclk/2).

But with the FLT values I get in FEI mode, I store into Filter Registers in SCM mode(to check whether this is working I purposefully stay in SCM mode (doesnot enter FEI mode)) I get around 8.5MHz which is unacceptable for LIN protocol.

Regards,

Denn.

[bigmac]

Hello Denn,

My understanding is that, if loss of lock occurs, the bus frequency will continue at approximately the same frequency as the locked frequency, i.e. the locking process will have adjusted the filter value, as previously discussed.  However, the stability will likely be insuffient to maintain SCI communications.  To minimize data loss, in the event of prolonged loss of lock, I guess the only alternative is to reset the MCU, to attempt to regain normal operation as quickly as possible.

As you have discovered, simply setting the filter value in self clocked mode will not allow serial communications to occur.  The ICG neeeds to be locked for reliable operation.  So the sooner entry to FEI mode is commenced after reset, the least data will be lost.  You might experiment whether altering the filter value results in lock occurring more quickly than with the default setting.

For a minimum period with loss of communications, you might forego ANSI initialisation of global variables, in favour of explicitly initiailizing the variables yourself, as they are used.  This will reduce the startup code, and provide for earlier selection of FEI mode, maybe by a millisecond or two, depending on the number of globals.  I assume it is possible to do other initialisation task prior to lock occurring.

Regards,

Mac

[Denn]

Hello Mac and Fabio,

Do you have an idea that when there is loss of lock, what could be the variation in busclock wrt 8 MHz.    If its 8MHz +/-2% then I feel its fine with LIN.

Ofcourse LOSS OF LOCK RESET is a good solution to come out of this situation.But I don't want reset the system unless its really required.

If we can find some alternative to this 'reset' solution,I would love to go for it.

So far I didnot get any answer for my query from Technical Support.They are still working on it.

Regards,

Denn

[bigmac]

Hello Denn,

On re-reading the ICG section in the datasheet, I think there is unlikely to be a loss of lock problem for FEI mode.  Entry to STOP mode with clock turned off will obviously cause loss of lock, but I would assume this does not apply in your case.  Variation of the internal reference trim value may also temporarily cause loss of lock, but this can be avoided if the trim value is written prior to selecting FEI mode.  Provided no ICG registers are affected, any loss of lock would be temporary, and lock would be quickly regained.

If it is possible for an external ESD event, or other or other transient interference condition to corrupt the the ICG registers, more than likely other registers will also be affected, so a reset will probably be dictated so as to initialise all registers.

The datasheet states -

Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast frequency lock when recovering from stop3 mode.

This would seem to imply that faster lock out of reset may also be possible by initialising the filter register, whilst in SCM, for a DCO frequency closer to the ultimate locked frequency.

I presume that the ICG would use a multiplier value N = 14 and a clock divider value R = 2.  For a DCO frequency of 16.0 MHz (8.0 MHz bus) this would imply that the reference clock will need to be trimmed for 250 kHz, rather than the nominal 243 kHz.

Regards,

Mac

[Denn]

Hello Mac,

You are right.Digitally-controlled oscillator (DCO) preserves previous frequency settings when running just out of lock.

My concern was during runtime due to some shock/vibration if the lock of ICG loses / MCU didn't lock initially, in that case I wanted to be sure that the MCU ran at desired 8MHz and hence wanted to know about the filter register relation wrt  fBUS.Also during runtime change in TRIM register, done to bring back the fBUS to the desired 8 MHz from a deviation of ~=  -2% (due to high temperature)  would result in loss of lock.Hopefully I may not need SCM mode settings.

To my query the FSL Support's reply was

---

"Here is the answer I got to my question regarding the SCM clock:

"Self Clock mode is a very particular case; it is intended to provide a clock that could help you to initialize the system in the abscense of another clock.The values for ICGFLT don't have a direct formula to be calculated;basically you write a value, check the output frequency and then adjust it writing a higher value to get a higher frequency or smaller to reduce it.

You also have to remember that Self Clock mode has poor accuracy; it could change a lot on all the voltage and temperature range, this is one more reason to avoid using it for something different than initializing the system.

Resuming the answer, there is no formula on how to calculate the ICGFLT register, you simply have to write it until you get the desired bus frequency.

It is also good to remember that SCM should be avoided for something different than system initialization since it has a poor accuracy."

So it seems that the accuracy of the SCM mode is not to count on.If you need it, calibrate it against a known external frequency.

---

Any way I decided to go without the SCM fBUS=8MHz.

Regards,

Denn

[fabio]

Hi Denn,

I don't know the relationship between the filter registers and the ICG output frequency, but have you considered using the FEI mode and let the FLL to adjust the frequency accordingly? Setting N=14 and R=2 you will have an ICGOUT=15.5MHz. Just read ICGFLTU and ICGFLTL to know the filter value.

By trimming the ICGIRCLK to a value of 250kHz you will get the desired 16MHz ICGOUT and 8MHz BUSCLK (or you can fine trim ICGFLTL to reach the 16MHz output).

Hope it helps,



Message Edited by fabio on 2008-03-31 03:06 PM

[Denn]

Hello Fabio,

My system is running in FEI mode (Bus clk= 8MHz).

But before the program control  hits ICG control registers (wherein the mode switch to FEI is done)the MCU will be running in default SCM mode and by default configuration of ICGFLTU and ICGFLTL = 0x00C0, I'll be getting 4 MHz Busclock.

I don't need this 4 MHz, instead I need 8MHz busclock right from the reset.

Trimming is done later in the code  to tune the internal oscillator to 250kHz so that I get the busclock of 8MHz .No issues there.

All I want is 8MHz just after reset and the documentations is insufficient for anyone to program the filter registers such that it gives the required frequency.

Regards,

Denn.

[fabio]

Hi Denn,

But you could read the FLT registers after FEI mode is engaged and then use the same value in the initialization code (before changing to FEI mode)...

I agree that the documentation is poor on this topic.

Best regards

[Denn]

Hi Fabio,

As you know the FLT registers determine the frequency in SCM mode.But I am not sure whether the FLT registers get updated once it enters FEI Mode.

But surely I'll check this and keep you updated you on this matter.

Thanks and regards,

Denn

[Denn]

Hi Fabio,

You are right, I read the values of FLT(locations 0x4C and 0x4D) registers in FEI mode at 8MHz.

Its showing 0x06CA-0x06CD.Seems like the bus frequency is updating this register even in FEI mode.

Conclusion: The values should be 0x06CA-0x06CD.

Thanks for great idea.  But I need the relationship equation for documenting.Anyway I have raised a service request they might provide some solution.

And Thanks again !

Regards,

Denn