@Eckhard:
thanks for your comment. Unfortunately theres no RTIACK Bit and even no RTI Status Register. But this one ( RTCSR ):
SECF — Second Flag
This clearable, read-only bit is set on every increment of the second
counter. When the SECIE bit in RTCCR1 is set, SECF generates a
CPU interrupt request. In normal operation, clear the SECF bit by
reading RTCSR with SECF set and then reading the second register
(SECR). Reset clears SECF.
1 = Second counter incremented
0 = No second counter incremented
Is this used to acknowledge the irq from the ISR ?
thanks.