Questions about S08ICSV3 (MC9S08QEx) Clock Generator

[Wingsy]

My objective is to get a fast stable BUSCLK (internal osc) from a QE8 as simple as possible. This is what I've read in AN3499 (Clock Options on the HC9S08 Family) about the ICS in section 2.1:

Table 4 shows that with DRS bits = 00 and DMX32=1 that I get a reference freq of 32.768K and a DCO output freq of 19.92M, which can give me a BUSCLK of 9.96M. It also states in section 2.1.5.4 (about the ICS Status & Control reg) that

"The register also contains the DCO maximum frequency bit (DMX32) that determines if a finely tuned reference frequency of 32.768 kHz is used. When using this reference, the DCO multipliers are greater when compared to general reference frequencies and this provides a fixed DCO output."

When I read "a finely tuned reference frequency..." it made me wonder WHO does this "finely tuned" thing, me via the trim bits, or Freescale in the chip? Table 4 makes me think it is independant of the trim bits.

Anyone have any experience using it this way? 

[bigmac]

Hello Wingsy,

My understanding is that the DMX32 = 1 setting is intended for use with an external 32.768kHz crystal reference, because of the proximity to the DCO upper frequency limit (with the increased multiplying factor).

When using the internal reference, I would tend to use DMX32 = 0 setting. so that the DCO frequency will remain within its operating range, even prior to the reference being trimmed.

Regards,

Mac

[PG1]

What BigMac is saying is correct...if you set DMX32=1 and use the internal oscillator you could violate timing requirements if the internal oscillator is trimmed higher than 32768Hz.

[Wingsy]

Thanks you two.