Hello,
Any data received by SCI1 (at the lower baud rate) may be immediately written to SCI2D register, from within the SCI1 receive ISR. SCI2 should always be ready to handle the new transmit data.
The potential problem will be the sending, via SCI1, of the data received by SCI2 - data can arrive at a faster rate than it can be re-sent. You will obviously need a FIFO (circular) buffer that is written by the SCI2 receive ISR, and is also accessed by the SCI1 transmit ISR. It would be up to the SCI2 receive ISR to ensure that SCI1 transmit (TDRE) interrupt became enabled wnen any new data was received.
What happens next will depend on the nature of the received data - whether the buffer can be made large enough to hold each data burst, and whether there is sufficient time between data bursts to re-send the data at the lowest baud rate.
If not, you will need to prevent butter overflow by the implementation of handshaking for SCI2. This handshaking may be of the "hardware" type, using CTS or DSR signals. Alternatively, "software" (Xon/Xoff) handshaking may be feasible. Whatever method you use, it will need to match that implemented within the target device.
Regards,
Mac
