QE128, small flash routines in C not operating

[CarlFST60L]

Hi all,

I have just put togehter some simple C code with the core functions copied from another thread. I cannot get the flash to erase or write.

I am thinking the problem is either to do with the paging in this processor (which i dont fully understand), or the timing. Otherwise I have no idea.

I have other working flash code in other processors using a far more complicated method (which I posted on here previously), but really want this to work as its far more simple.

Code:

#include <hidef.h> /* for EnableInterrupts macro */#include "derivative.h" /* include peripheral declarations */word wTemp = 0;                 //General usage wordbyte bTemp = 0;                 //General usage bytevoid InitFlashRoutine(void);    // match number of bytes above.void FlashInit(void);byte FlashErasePage(word page); byte FlashProgramByte(word address, byte data);const unsigned char ROM_PGM[7]  = {  0xf7,                // sta ,X      FSTAT  0x44,               // lsra -  delay and convert to FCCF bit0xf5,               // Bit X ,fstat0xf5,               // Bit X ,fstat0x27,0xfd,          // BEQ *-10x81                // RTS}; volatile unsigned char PGM[7]  = {  0xf7,                // sta ,X      FSTAT  0x44,               // lsra -  delay and convert to FCCF bit0xf5,               // Bit X ,fstat0xf5,               // Bit X ,fstat0x27,0xfd,          // BEQ *-10x81                // RTS}; void main(void) {  PTBDD_PTBDD2 = 1;   //Pin used for debug  PTBD_PTBD2 = 0;     //LED1 on on first power up  PTBDD_PTBDD3 = 1;   //Pin used for debug  PTBD_PTBD3 = 1;   //LED2 off     //Setup bus to run at 19.925Mhz//ICSC1 remains default (Internal reference with FLL enabled)//ICSSC setting, 39.85Mhz//DRST = 01 = Mid range//DMX32 = 1 = Accurate internal xtal//Internal reference selected//Output of FLL Selected  ICSSC = 0b01110000;  ICSC2 = 0b00000000;   //Bus div 1//Not sure how this is suppose to be done now as there is no FLL lock... Just created a about a short delay to be sure//  while(!ICGS1_LOCK) __RESET_WATCHDOG();   //Wait for lock before allowing software to startup//Loop for wTemp*2^8  wTemp = 1000;  bTemp = 0;  while(--wTemp){    while(++bTemp)    __RESET_WATCHDOG();   //Wait at least some time for the clock to stablise, really should be 1mS  }  PTBD_PTBD2 = 1;     //LED off once running    EnableInterrupts; /* enable interrupts */  /* include your code here */  InitFlashRoutine();       //Ensure RAM is loaded correctly  FlashErasePage(0x8000);  FlashProgramByte(0x8000, 0xCC);    if((*((byte *)0x8000)) == 0xCC) PTBD_PTBD3 = 0;     //LED on if programming success  for(;;) {    __RESET_WATCHDOG(); /* feeds the dog */  } /* loop forever */  /* please make sure that you never leave main */}void InitFlashRoutine(void)    // match number of bytes above.  {  PGM[0] = ROM_PGM[0];  PGM[1] = ROM_PGM[1];  PGM[2] = ROM_PGM[2];  PGM[3] = ROM_PGM[3];  PGM[4] = ROM_PGM[4];  PGM[5] = ROM_PGM[5];  PGM[6] = ROM_PGM[6];    }//      -      -      -      -      -      -      -      -      -      -      -      -      -//This must be setup based on the clock settings#define initFCDIV 0b01001101                //FLASH clock divider (setup for 20Mhz Bus)//                  ||||||||//                  |||||||+-DIV0 \//                  ||||||+--DIV1 |//                  |||||+---DIV2 >-- divide by (12+1)//                  ||||+----DIV3 | BUSCLK/(8*12)~=(192.3Khz)//                  |||+-----DIV4 |//                  ||+------DIV5 ///                  |+-------PRDIV8 -- divide (prescale) by 8//                  +--------DIVLD --- read-only statusvoid FlashInit(void){  while(FSTAT_FACCERR) FSTAT_FACCERR = 1;             //Make sure error is cleared before setting up the divider      if(!FCDIV_FDIVLD) FCDIV = initFCDIV;                 //set fFCLK = about 200kHz (if not already setup i.e. on warm boot)  FPROT_FPOPEN = 1;                                   //No flash protection  FPROT_FPS = 1;                                      //No flash protection}//      -      -      -      -      -      -      -      -      -      -      -      -      -byte FlashErasePage(word page) {      asm {      TPA         ; Get status to A      PSHA        ; Save current status        SEI         ; Disable interrupts      LDA  #0x30      STA  FSTAT  ; Clear FACCERR & FPVIOL flags      LDHX  page      STA ,X      ; Save the data      LDA  #$40   ; Erase command      STA  FCMD      LDA  #FSTAT_FCBEF_MASK      LDHX @FSTAT       JSR  PGM      PULA        ; Restore previous status      TAP   }      return (FSTAT & 0x30);  }byte FlashProgramByte(word address, byte data) {      asm{      TPA        PSHA        ; Save current status        SEI         ; Disable interrupts      LDA  #0x30      STA  FSTAT  ; Clear FACCERR & FPVIOL flags      LDHX  address      LDA  data      STA ,X      ; Save the data      LDA  #$20   ; Burn command      STA  FCMD      LDA  #FSTAT_FCBEF_MASK      LDHX @FSTAT       JSR   PGM      PULA        ; Restore previous status      TAP   }      return (FSTAT & 0x30);  }

 

Message Edited by CarlFST60L on 2009-01-14 02:36 AM

[bigmac]

Hello,

There appear a couple of possible issues -

It might be possible that a COP reset could occur during the erase process, whilst within the RAM based routine.  It is probably a good idea to periodically clear the COP timer within this routine.

You may also be correct that there is a paging issue with the QE128.  I notice that your test code addresses the paging window at 0x8000.  Perhaps carry out your initial tests at some other flash location, not dependent on the PPAGE setting.

The following code snippet does implement  the clearing of the COP timer.  Also shown is an alternative way of copying the RAM based code from flash, handled as a compiled function rather than as a variable.  The FLASH_ROUTINE segment also needs to be placed within the PRM file, making use of the RELOCATE_TO command.


extern char __SEG_START_FLASH_ROUTINE[];
extern char __SEG_SIZE_FLASH_ROUTINE[];

/* Private function prototype */
#pragma CODE_SEG FLASH_ROUTINE
void Flash_Cmd( void);
#pragma CODE_SEG DEFAULT

/*****************************************************************************/
#pragma CODE_SEG FLASH_ROUTINE

/* This function is loaded to RAM, and executed from there.
   The size of the function is 10 bytes.
   On entry, ACC must contain FCBF mask value (0x80),
   and H:X the address of FSTAT register */

void Flash_Cmd( void)
{
   __asm {
      STA  ,X     ; wp   Commence flash command
      LDA  #$70   ; (2)  FCCF|FACCERR|FPVIOL mask
L1:   STA  SRS    ; (3)  Reset COP required for page erase
      BIT  ,X     ; rfp  Test command status
      BEQ  L1     ;      Loop while incomplete & no error
   }
}

#pragma CODE_SEG DEFAULT
/*****************************************************************************/
/* Copies Flash_Cmd() function into RAM, with steps documented in Tech Note 228
   Start_data refers to the begining of the flash block to be copied.
*/
#define Start_data   __SEG_START_FLASH_ROUTINE
#define Size_data    __SEG_SIZE_FLASH_ROUTINE

void CopyInRAM(void)
{
   char *srcPtr, *dstPtr;
   int count;

   srcPtr = (char *)Start_data;
   dstPtr = (char *)(void *)&Flash_Cmd;
   for (count = 0; count < (int)Size_data; count++) {
      *dstPtr = *srcPtr;
      dstPtr++;
      srcPtr++;
   }
}

Regards,
Mac

[CarlFST60L]

Thanks for the reply Mac.

I dont think COP is an issue as the LED flash's on boot, which only happens once.
RE Page issue, I have tried address 0x4000, 0x8000 and 0xC000.  Also, I can read the address using the method in the code, and, if i step through the code, it appears to read the correct address's.

I have quite a few products in production which use a similar method to which you posted. When I copied that code over to the QE128, nothing worked as expected. So, I started searching and came across another thread which had some far more effectient and simple code so decided to use that, but had the same result, still no flash erase/write.

I tried various ideas, but still no luck on this QE128. I assume its something to do with this QE128 as similar routines work fine in SH8, QD2, GT32, AW32 etc.

[CarlFST60L]

I tested this on a GB60, and it worked. There is one mistake in the code i posted, it needs FlashInit(); added after InitFlashRoutine();

The only other thing i changed was:

Used:
while(!ICGS1_LOCK) __RESET_WATCHDOG();   //GT32 Wait for lock before allowing software to startup
instead of the count delay of 1 second or so

I also changed the clock speed to 4.32Mhz and initFCDIV to match.

so, i guess the problem must be either the bus speed running @ 19.925Mhz is a problem, or, the FLL isnt getting lock quick enough (I tried waiting 10 seconds to be sure, and it still didnt work).

I have tested the 19.925Mhz bus speed and it appears to be exactly that, 19.925Mhz.

so im lost.

 

[CarlFST60L]

I have confirmed that the bus is running at 19.925Mhz by doing a bset/bclr on an output and multiplying the result by 5.

So, I think that rules out the bus rate being a problem.

[TurboBob]

A couple things,  it appears that you have not locked the flash,  unless there is code not shown in your post.

I see you caught the FCDIV omission.

The HiWave debugger will not display the flash changes unless you set it up as suggested in the one of the miniRAM threads.

Once I fixed the debugger, I was able to debug and validate my flash functions. 

I have not used the QE part,  but I have the JM60 working with the short RAM routines.

Good luck.

Bob

[CarlFST60L]

thanks for the reply,

the flash should all be unprotected if my understanding is correct. Which I believe is correct in my sample code.

I have tested this code on a GB60 and it works fine! But still nothing on the QE128.
The only difference was the clock speed for the GB60 and FCDIV (slowed to 4.32Mhz as I had that from some other software).

Everything else was identical. I have also tried 2 x QE128's, one had nothing but 3.3V connected, gnd, BDM pins.

Is there an issue with paging? From what I understand paging has nothing to do with this, but i cannot see any other reason this wouldn't work (other than the bus speed being 19.925Mhz which shouldnt be a problem)

Also, I have done this with no BDM connected, tried 0x4000, 0x8000 and 0xC000.


Message Edited by CarlFST60L on 2009-01-16 05:29 AM

[kef]

Carl,

you init FPROT register this way:

  FPROT_FPOPEN = 1;                                   //No flash protection
  FPROT_FPS = 1;                                      //No flash protection

This way you are write protecting 126kB of flash. Is it what you want?

Flash routines from your first thread message (PGM and two Flashxxx routines) are working OK for me on QE128.

[CarlFST60L]

Just wondering what I can do next. I have tried the software, I have no idea why I can get 4 other processors working and not the QE128. What do I do now?

[CarlFST60L]

Please, can someone help.

We have tested this software in 3 other S08 processors (AW32, GB60, GE8) and it works first time every time no problems. The only difference when running QE128 is FCDIV, FBus and Paging.

I dont do anything with paging at all as we dont currently need it, though could be the problem?

We have also been supplied sample C code for the QE128 dev which DOES NOT WORK, it compiles WRONG, it jumps to the WRONG address when calling flash. So that was no help at all.

Has anyone got ANY code that works in QE128 they can share? Or can anyone tell me if my my settings for FCDIV, FBUS and Paging are ok as surely this is the problem

The mask revision is 1MJ11, codewarrior is the latest downloaded version (6.2)


Message Edited by CarlFST60L on 2009-01-23 03:31 AM

[pbouf]

Did you get any sample code to resolve your problem?

I am running in the same problem.

[CarlFST60L]

Also, I tried various address's, 0x8000 happened to be the last. I also tried a couple without the BDM.