Hi all,
I believe I have found 2 problems with P&E Micro's ICS08QT/QY ICS V1.16
The first is that the OSC2EN bit of PTAPUE register is implemented in reverse.
The second is that level sensitive KB interrupts are implemented for both levels, i.e. interrupt triggers constantly.
Here is the minimal code that exposes both problems:
$Include 'qtqy_registers.inc'
ORG $F800
* compile this then start simulator on this
* issue var porta
* issue var ptapue
* issue inputa ff
* now step through code
Start NOP ;at this point porta in variables window shows %00111111
* ;this is correct as only lower 6 bits are implemented
lda #$00 ;keeps simulator quiet when interrupt occurs
ldhx #$0000 ;ditto
CLR PORTA ;not really required here
mov #%00000000,DDRA ;Port A all ins
mov #%00111111,PTAPUE ;pullup all
NOP ;at this point porta in variables window shows %00101111
* ;this is wrong as bit 4 should work as an input
mov #%10111111,PTAPUE ;pullup all and enable OSC2 on PTA4
NOP ;at this point porta in variables window shows %00111111
* ;this is wrong as bit 4 should be outputting OSC
* ;now continue to expose next problem
bset 1,KBSCR ;mask keyboard interrupts
bset 0,KBSCR ;set to edge and low level sensitive
* ;if you comment out the above line edge sensitive KBI works as advertised
bset 2,KBIER ;enable ints on A2
* blah,blah
bset 2,KBSCR ;ack int just in case
bclr 1,KBSCR ;unmask kbd ints
CLI ;as soon as you get to here you will be locked in KBI int no matter what
* ;level is on A2
bra *
kbi_int
BSET 2,KBSCR ;ack int
NOP
rti
org $FFE0
dw kbi_int
org $FFFE
dw Start ; Reset
This is the current version (i believe) and seems to be a couple of years old.
Has anybody else experienced this?
Or am I missing something?
BR Peg