I'll assume you mean the one that works is an S08QG8.
I wonder if this is a difference between TPM v2 and TPM v3.
QG8 is a V2 TPM
The SL8 reference manual TPM chapter heading says the timer is V2 but then talks about the differences between V2 and V3 at the end of the chapter.
V3 has a difference in the latching mechanisms for the joined bytes of channel and modulo registers. I wonder if it has anything to do with this?
In your SL8 code, I wonder if the "coherency" mechanism is being reset by writing the status and control register right after writing the channel registers.
In the notes for the V3 TPM, they suggest that maybe you should write the channel registers and then read them in a while loop comparing them to the expected values until the compare read proves they've been updated. Then you could write your Status and Control registers.
JD