MC9S08QB4; Using a 100kHz external low-power crystal in FBELP mode, but can not find recommended information

[admin]

Hi Guys, I'm still having a little problem in timing/clocking this µC in Ultra-Low-Power Mode.

Short background: trying to set an output-pin (at PTB) as fast as possible, on-state to off-state within 60µs (or a bit less) in FBELP. This is not possible with a 32,768kHz crystal on XTAL/EXTAL. I'm using assembler for faster execution, but the shortest interval I can program is 250µs. Even if I use a 38,4kHz crystal to shorten interval (on-/off-state) I can not reach 60µs, it's 130µs. I already tried 100kHz as external crystal and it is running fine, but...

Now my little problem and question: datasheet, manual, CodeWorrier and application notes don't even say it is possible to use an 100kHz external crystal in FBELP. Maximum is 38,4kHz.

e.g. AN3499 “Clock Options on the HC9S08 Family“ don't even borders the device MC9S08QBx but concerning the family?! Nice!

I realy need a suitable statement.

Any helpful ideas??? Thanks for answering.

[bigmac]

Hello,

Using a 32.768kHz crystal in FBELP mode will result in a bus frequency of 16.384kHz, or a bus cycle period of 61 us.  Assuming that you change the output pin state using a BSET or BCLR instruction, this will take 5 bus cycles, or 305 us.

To use a crystal of higher frequency than 38.4 kHz, you will need to select high range mode, with a minimum allowable frequency of 1 MHz, or alternatively you can make use an external oscillator anywhere below this frequency.  For a 100 kHz oscillator frequency, the maximum bus frequency would be 50 kHz, for a bus cycle period of 20us.

Using a 1 MHz or 2 MHz crystal or ceramic resonator in FBELP mode, would produce a minimum bus period of 2us and 1us, respectively.  This period may be increased "on the fly" by a factor of 2, 4 or 8, by adjustment of BDIV within the ISC module.  This would give more practical bus frequencies for your application.

Another approach might be to use FEI mode, possibly in conjunction with a BDIV factor of 8, for a bus frequency of about 1 MHz.  It may also be feasible to use Stop3 mode during the time between transition events, to greatly reduce the average current draw.

Regards,

Mac

[admin]

Good morning Mac,

great thanks for answering so detailed and fast.

-to 1.

Well, you are right, using BSET and BCLR options to get 5 bus cycles, but I´m using a simple ASM { MOV (#0...1, PTDB) } inside C-Code and this results in 245us and as you know, this interval is not short enough.

-to 2.

Yes, you're right again, I did this already and I used a 1.8432MHz crystal to definitely stay below 125kHz for the internal bus clock in LPRun-Mode. Internal bus clock it's now 115.2kHz, clock range is high frequency (1-16MHz), oscillator operating mode is LowPower and current consumption is 3 times higher then using a 32.768kHz crystal. Sh...t!

Using an external oscillator (100kHz) would also increase current consumption and it additionally would increase needed space for more components (to drive such an oscillator). That space, I really don't have.

I think it's always more suitable to use an external crystal to save power at all events. What do you think?

-to 3.

As you may realized now, my biggest challenges are power consumption and component size and so it might be a kind of logic to stay in LPRun. Well, there are two low power strategies, high frequency pulsed version where you partial power down your system or (that I want to use) long-term Low-Power-Mode.

-to 4.

Sure, this is an option. I already tested some settings. In the End, it can be that I should do this. I thought about using this pulsed strategy in FEE with a 32.768kHz crystal. My problem, I have to switch off all peripherals, also ICSERCLK and so it is impossible to wake-up fast from stop3mode.

I'll test this today.

Q5:

You know, the devil is in the detail. But I can't find him!? What I don't understand is, what is the problem with a 100kHz crystal in FBELB? The Reference Manual of MC9S08QB4 is saying, that you can use an external reference clock source, it can be a crystal or resonator or another external source. It also says that every “external reference clock with frequencies between 31,25.25kHz to 40MHz in all modes” is supported by the ICS module (RM chapter 11.4.7, s. 168).

Best Regards,

Brambostel

[bigmac]

Hello Brambostel,

All MCUs that incorporate an ICS module have a low range upper frequency limit of 38.4 kHz, when using a crystal.  I notice that other MCU types that use a somewhat different ICG module have an upper frequency limit of 100 kHz, but may possibly have higher current draw.  Generally, these MCU will have a minimum operating voltage of 2.7 volts, rather than 1.8 volts.

Recovery from Stop3 mode will be much faster using FEI mode, compared with the startup period required by an external crystal for FEE or FBELP modes.  A low frequency crystal will be much slower than a high frequency crystal.  However, the external reference may be left running during stop3 mode to give immediate recovery.  This will add nominally 1 uA to the stop mode current draw for the low range setting.  By comparison, enabling the internal reference during stop3 mode will add 70 uA.

I might consider 32.768 kHz crystal, FEE mode, ERREFSTEN = 1,  bus frequency ~1 MHz (BDIV = 3), and use of Stop3 mode.

Regards,

Mac

[Brambostel]

Hi Mac,

did some interesting tests on Friday. Now it seems that I reached almost the same level of power consumption as using FBELP. I have to make some more tests with all of the hardware to be sure. It seems that I don't need this 100kHz crystal anymore.

I'm using the already mentioned low frequency low power crystal (32,768kHz) in FEE-mode and a internal clock of 1,04MHz. Recovery from STOP3 is short enough to produce a 130Hz interval via a simple RTC interrupt routine. I really have to leave internal and external clock in off-state during STOP instruction to save power. But as you can see, it is not a problem.

Best Regards,

brambostel