MC9S08GT60 RTI not working with Internal Oscillator

[alex_spotw]

Hi:

I'm using the MC9S08GT60 RTI with CW 3.1 and Processor Expert Beans, and an External Crystal of 16MHz.

When I select the RTI to work from the External Clock Oscillator, it works fine (I got the periodic interrupts). However, when I select to use the Internal Oscillator, I never get the interrutps. The PE Bean is writing the correct value into the SRTISC registert (0x17) for the internal oscillator selection, but no interrupts. The code is there to process the interrupt (write the ack), but it never seems to go to the ISR for the RTI.

Is there something that I'm missing (initialize other register/etc) so that the RTI can work from the Internal Oscillator?

Thanks!

Alex

[desponia_]

S12 Question moved to S12 Board. This board is for 8 Bit only and MC9S12DG128 is 16 Bit.

[ProcessorExpert]

Hi,

I suppose that you want to use RTI in run (normal operating) mode...in the mode RTI don't run with internal oscillator - Manual for GT60 p. 67 ... or a PE bean warning :

+TI1

 +Warning: RTI device won't run in Run mode - Internal oscillator is selected as clock source!

Regards, Processor Expert Support

http://forums.freescale.com/" target="_blank 

[alex_spotw]

Hi:

Thank you for your answer.
Effectively, p67 indicates that the External Clock can be used only for the RTI in Run and Wait Modes.

However, I don't get the Warning that you mention when I select the Internal Oscillator. In fact, no warning at all. That'w why I continued trying to use it.

If I select the External Clock I do get a warning:


+TI2
+Warning: RTI device won't run in Stop2 mode - External clock is selected!

I'm using PE 2.95.03 for HC(S)08. Which version are you using?

Regards,

Alex

Message Edited by alex_spotw on 02-23-200601:48 PM

[peg]

Hi all,

Woops it's pretty darn clear...

"In run and wait modes, only the external clock can be used as the RTI's clock source. In stop2 mode, only the internal RTI clock can be used."

I would like to know the reason behind why the RTI does not have access to this clock in run mode.

Some reasons why you would want this.

With a high frequency xtal the divider is not enough!

With no xtal (SCM, FEI) you have got no RTI at all (in run mode).

As to the warning (or lack of) from Processor Expert:

You may be using the RTI purely as a method of exit from STOP mode so the setup would be valid. As is often the case the answer is to RTFM!

Peg

[peg]

Hi Alex,

If you have got it working with the external osc, then it should just be a matter of changing SRTISC from 0x37 to 0x17. The RTI period will change from 2ms to 1s though. Why don't you try to do a clock select change "on the fly" in your code? If it stops giving interrupts then your internal RTI clock is broke.

BTW there is an error in the GB60 manual Rev2.3 at 5.8.6 (SRTISC) it says there is 3 unimplemented bits, there is only 1!

BR

Peg

[alex_spotw]

Hi Peg:

Thank you for your idea. I did change it on the fly, and goes from Interrupting every 2ms to not interrupting. I tested with two different devices, obtaining the same results.

I wonder if the GT60 does not implement the Internal Oscillator for the RTI or if the mask (3L31R) has a problem with this oscillator.

Has anybody get the RTI working from the Int Osc in the GT60 before?

Regards,

Alex R.

[peg]

Hi Alex,

Not what you want to hear, but I confirm your observation using the code below on a GB60 with 3L31R.

BTW 32kHz xtal.

NOLIST
#include "9S08GB60v1rdp.inc"
.LIST

 ORG RamStart
counter  rmb 1
stat rmb 1

 ORG RomStart

 lda #(mCOPT+mSTOPE+mBKGDPE)
 sta SOPT   ;disable COP
 mov #0,counter
 mov #%00001111,PTFD
 mov #%00001111,PTFDD
 mov #mPTAPE4,PTAPE
 clr stat
 ldhx #$0000
*********** Set-up ICG to clock the bus at 18.8 MHz **********************

  MOV #(mMFD2|mMFD1|mMFD0),ICGC2 ;sets MFD divider
  MOV #(mREFS|mCLKS1|mCLKS0),ICGC1  ;
  BRCLR LOCK,ICGS1,*  ;loop until FLL locks
 jsr RTI_init
 CLI    ;enable ints
loop1 brset PTAD4,PTAD,loop2
 brset 0,stat,loop1
 bset 0,stat
 lda SRTISC
 ora #mRTICLKS
 sta srtisc
 bra loop1

loop2 brclr 0,stat,loop1
 bclr 0,stat
 lda SRTISC
 eor #mRTICLKS
 sta srtisc
 bra loop1

RTI_init:
* lda #(mRTICLKS+mRTIE+mRTIS2+mRTIS1+mRTIS0)
 lda #(mRTIE+mRTIS2+mRTIS1+mRTIS0)
 sta SRTISC
 rts

RTI_Handler:
 lda SRTISC
 ora #mRTIACK
 sta srtisc
 inc counter
 lda counter
 coma
 sta PTFD
 rti

 ORG $FFCC
 DC.W RTI_Handler ; RTI

 ORG $FFFE
 DC.W ROMStart ;

BR

Peg

[alex_spotw]

Hi Peg:

I submitted a Service Request to the Freescale Support, regarding this issue. We have to wait and see any response.

Regards,

Alex