MC9S08DZ60CLC Sector Erase Time

[rsheldon]

My application requires a fast sector erase/write time to function as a counter.  The measured erase/write time on my MC9S08DZ60CLC has been consistently about 3ms, however, the datasheet (p. 53) states that a sector erase by itself takes 20ms.  How is this possible?  Did I miss something or does the microcontroller perform better than it's supposed to? 

[kef]

Looks like something is wrong with FCDIV setting. Timing is shorter almost 8 times, as if PRDIV8 bit was not set... Did you note that according to DZ60 datasheet FCDIV is write once register? This means you can't set up DIV5:0 bits first, and then set up PRDIV8 bit. All FCDIV bits should be written at once.

[rsheldon]

I should explain also that I am just learning assembly language and am trying to understand how a former employee coded our chip.  With that said, I took a look at the code and I found one line containing FCDIV that reads as follows:

 ; FCDIV: DIVLD=0,PRDIV8=0,DIV5=1,DIV4=0,DIV3=1,DIV2=0,DIV1=0,DIV0=1
            LDA     #$05 ;#$45       ;#$05 is for low
            STA     FCDIV                  ; Set clock divider

I hope this is useful information, if not let me know and I can scrounge up some more code.

[bigmac]

Hello,

The required FCDIV setting will depend on the bus frequency you are using - the divider setting must be such that a flash clock frequency within the range 150-200 kHz is generated. A divider setting of 5 will produce a division ratio of 6, implying that the bus clock is within the range 0.9-1.2 MHz.  However, I would suspect that this is probably not the case.

For example, if the bus frequency were 8 MHz, a divider setting of decimal 39 would be necessary.

Regards,

Mac

[rsheldon]

This appears to be the section of code in question:

;;; Drop down to 4MHz

        ; MCGC2: BDIV=0,RANGE=0,HGO=0,LP=0,EREFS=0,ERCLKEN=0,EREFSTEN=0
        ;CLR     MCGC2                  ; Set MCGC2 register
            MOV     #$40,MCGC2
        ; MCGC1: CLKS=0,RDIV=4,IREFS=1,IRCLKEN=1,IREFSTEN=0
            MOV     #$1E,MCGC1       ;#$26 for low #$06 for high
        ; MCGC3: LOLIE=0,PLLS=0,CME=0,VDIV=1
            MOV     #$01,MCGC3             ; Set MCGC3 register

        ; ### Init_FLASH init code
        ; FSTAT: FCBEF=0,FCCF=0,FPVIOL=1,FACCERR=1,FBLANK=0
            LDA     #%00110000
            STA     FSTAT                  ; Clear error flags
        ; FCDIV: DIVLD=0,PRDIV8=0,DIV5=1,DIV4=0,DIV3=1,DIV2=0,DIV1=0,DIV0=1
            LDA     #$05 ;#$45       ;#$05 is for low
            STA     FCDIV                  ; Set clock divider

It looks as if he loaded the accumulator with 0x05 and stored that value in FCDIV, but the comment shows he's setting FCDIV as 0x19. Am I interpreting this correctly?

[bigmac]

Hello,

It would appear that the code you have posted has been generated by the PE initialisation tool.  However, the FCDIV setting has then been altered without the comment line being updated.

  ; FCDIV: DIVLD=0,PRDIV8=0,DIV5=1,DIV4=0,DIV3=1,DIV2=0,DIV1=0,DIV0=1
           LDA     #$05 ;#$45       ;#$05 is for low
           STA     FCDIV            ; Set clock divider

 The original PE initialisation gives a value of $29 (decimal 41) for a division ratio of 42.  With this value, a trimmed bus frequency of nominally 8 MHz would give a flash clock frequency of 190 kHz, which makes allowance for a bus frequency tolerance of +/-5%. (This allowance would not be necessary if an external crystal reference were utilised.)

Accepting that the new bus frequency has been trimmed to 4 MHz, and allowing a similar frequency tolerance, the required division ratio would be 21.  Therefore the FCDIV setting should be $14 (20 decimal).

I suggest that you check the MCG register settings to determine whether the bus frequency is actually 4.0 MHz, as the initial comment suggests.

Regards,

Mac