Hello,
I made a further attempt to understand the operation of the filter algorithm, and it appears that a standard form of filter is actually used, that gives results close to a single RC circuit in the analog domain. In fact the filter is applied twice, to give the effect of two cascaded CR circuits with equal time constants.
The registers IY and IZ are the filtered values, that must remain static, and must be initialised. Also keep in mind that shift right 6 places is identical to divide by 64. So the calculation of each updated filtered value may be derived.
IY = IX + IY*63/64
IZ = IY + IZ*63/64
Each filtered value is 64 times greater than the final mean (20-bit) value. This is why IZ needs to be divided by 64. I am not sure why the final value has then been incremented by 2.
I also observe that the dword registers IX, IR and IT are for temporary use only, and only a single register (say IX) is actually necessary. This should reduce the dedicated RAM requirement to 12 bytes.
I have attempted to "clean up" the code, but the attached code remains untested so there might possibly be some overlooked errors.
Regards,
Mac
Message Edited by bigmac on 2009-05-14 10:21 PM