void test(void){ DisableInterrupts; // 8 data, 1 stop, no parity SCIC1 = 0; SCIC2 = 0; SCIC3 = 0; SCIBD = 128; // set baud to 8 SCIC3_TXINV = 1; SCIC2_TE = 1; __RESET_WATCHDOG(); ICGC2 = 8; // Generate a reset request on loss of clock. ICGC1 = 0b00110100; // FBE mode, fbus=16,384 Hz, clock monitor enabled while(ICGS1_CLKST != FBE) __RESET_WATCHDOG(); RS485_TX_EN(); // set TXCS pin SCID = 1; // send a two falling edges have period one second over TX pin while(!SCIS1_TC) __RESET_WATCHDOG(); RS485_TX_DIS(); // clear TXCS pin asm("dcb 0x8D"); // reset the mcu }
Transmission Complete Flag
— TC is set out of reset and when TDRE = 1 and no data, preamble, or breakcharacter is being transmitted.
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
TC is cleared automatically by reading SCIS1 with TC = 1 and then doing one of the following three things:
• Write to the SCI data register (SCID) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to SBK in SCIC2
Isn't the routine sending a break character, which is what is seen on the oscilloscope?
If you change the
RS485_TX_EN(); // set TXCS pin
to
for (;SCIS1_TC == 0;
and check what happens.
Regards,
Ake
#define RS485_TX_DIS() {PTBD_PTBD3 = 0; PTBDD_PTBDD3 = 1;}#define RS485_TX_EN() {PTBD_PTBD3 = 1; PTBDD_PTBDD3 = 1;}
RS485_TX_EN(); // set TXCS pin SCID = 1; // send a two falling edges have period one second over TX pin
while(!SCIS1_TC) __RESET_WATCHDOG();
Sten must be right. From LC60 SCI module docs:
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.Refer to Section 12.3.2.1, “Send Break and Queued Idle,” for more details
S12X SCI behaves exactly the same, though TE bit isn't documented equally well. It's interesting what transmission is in progress when we set TE=1 for the first time :smileyhappy:, but it seems that any TE rising edge makes SCI sending idle character.
BasePointer, regarding reading SCIS1. Your while(!SCIS1_TC) is OK for reading SCIS1 register, but it comes after you first time write to SCID register. Maybe you read it somewhere earlier then in the test() routine?
[SCID=?] followed by [while( !SCIS1_TC) ;] should be OK, provided you read SCIS1 with SCIS1_TDRE set at least once before. You should clear TDRE before writing to SCID, and the only way to do that is reading TDRE==1 and writing then SCID. You say the result is the same if you read SCIS1 before SCID or not. You also said previously that you see no TX output with BDM not connected. Did you recheck if you see now TX output with no BDM connected?
Regarding unwanted idle character and delay between TXCS and TX. After writing TE=1, you should delay setting TXCS for idle character time. Try 1) setting baudrate divider to min value of 1, 2) enabling TE=1, 3) waiting for full character time at fastest baudrate, 4) setting baudrate divider to value you want (128). At least this works on S12XD.
void test(void){ DisableInterrupts; // 8 data, 1 stop, no parity SCIC1 = 0; SCIC2 = 0; SCIC3 = 0; SCIBD = 1; // set baud to 1024 SCIC3_TXINV = 1; SCIC2_TE = 1; while(!SCIS1_TDRE) __RESET_WATCHDOG(); // added with kef's warning ICGC2 = 8; // Generate a reset request on loss of clock. ICGC1 = 0b00110100; // FBE mode, fbus=16,384 Hz, clock monitor enabled while(ICGS1_CLKST != FBE) __RESET_WATCHDOG(); Delay20uS(1); // it waits about 15ms at that bus freq SCIBD = 128; // set baud to 8 RS485_TX_EN(); // set TXCS pin SCID = 1; while(!SCIS1_TC) __RESET_WATCHDOG(); RS485_TX_DIS(); // clear TXCS pin asm("dcb 0x8D"); // reset the mcu }