Instruction cycle counts in HC08, HC05, HC11 chips

[Benedek]

The documents for HC08, HC05, and HC11 all seem to indicate that a conditional jump instruction takes a fixed number of cycles regardless of whether the jump is taken or not.  Has anyone confirmed this behavior?  I've seen documents from other companies neglect to mention this, and I need to know for sure the timings of Motorola's 8-bit cores.

Please don't respond with guesses, educated or otherwise, as that only furthers the problem.  I'd like to hear from people who know from experience.

Help in this matter will be much appreciated. 

Thanks,

..Ben

[bigmac]

Hello Ben, and welcome to the forum.

Certainly for the HC05, HC08 and HCS08 devices, the conditional relative branch instructions take three bus cycles to complete, independent of whether the branch is taken.  Other branch instructions, such as CBEQ and DBNZ (applicable to the HC08 and HCS08) may have different cycle counts, but again will be independent of whether the branch is taken.

You can confirm this by using full chip simulation within CW.

Note that, for many instructions, you may need to distinguish between HC08 and  HCS08, because of differing cycle counts.

Regards,

Mac