Hi Wings,
As I am considering a IIC device on a GT16 project I took a look at what you discovered here.
I duplicated the test you did using SCM on a GB Demo board and here I found similar results to what you did in that the status went through many intermediate states but settled on A3 earlier than it should have.
Then I decided that SCM is not the best mode to use so I set up the ICG to use the on board 32KHz xtal and step it up to 4.19MHz.
I then used /40 like you to achieve a IIC clock of 104.825KHz.
This come out on the scope at 86us for the 9 bits as expected (85.857us calc)
Now I get nearly exactly the pattern of status that you describe (just with a 1 sample jitter sometimes)
BUT the settle to status A3 occurs after 24/25 cycles which is 10us after the ninth bit, which pretty much makes sense.
Now looking back at your results it seems that your clock may be slower than you think it is. I have no explanation for the strange status states of SRW and RXAK though.
80 TCF Before start
80 TCF Start
80 TCF
A0 TCF, Busy
21 Busy, RXAK
25 Busy, SRW???, RXAK
25 Busy, SRW, RXAK
25 Busy, SRW, RXAK
25 Busy, SRW, RXAK
25 Busy, SRW, RXAK
24 Busy, SRW
24 Busy, SRW
20 Busy
20 Busy
21 Busy, RXAK
21 Busy, RXAK
21 Busy, RXAK
25 Busy, SRW, RXAK
25 Busy, SRW, RXAK
24 Busy, SRW
24 Busy, SRW
20 Busy
20 Busy 9th clock done, no ack as no slave
20 Busy
21 Busy, RXAK
A3 TCF, Busy, IICIF, RXAK
A3 etc
Here is my entire test code:
Code:$Include "9S08GB60v1rdp.inc" org RomStart*********** Set-up ICG to clock the bus at 4.193 MHz **********************start CLRA MOV #%00000000,ICGC2 ; MOV #%00111000,ICGC1 ;lockchk sta SRS BRCLR LOCK,ICGS1,lockchk ;loop until FLL locks mov #$07,IICF ;/40, 10 hold LDHX #$100 MOV IICS,X+ ;WHAT IT IS B4 WE FOOL WITH IT. MOV #%10110000,IICC ;IICEN+MST+TX = START CONDITION. MOV #$CC,IICD ;SEND ADDRESS BYTE.SAVSTAT LDA IICS ;3 STA 0,X ;2 SAVE STATUS REG. AIX #1 ;2 FROM $100 AND UP. STA SRS ;4 (DO THIS THE LONG WAY AND CPHX #$800 ;3 CONSUME EXTRA TIME TO REDUCE BLO SAVSTAT ;3 THE NUMBER OF DATA POINTS.) ;= 17CYC * 238nS = 4.05uS/looploop NOP ;BREAKPOINT HERE. sta SRS bra loop org $fffe dw start