ICS question: How to use 16MHz crystal? - MC9S08QG8

[Helmut]

Hello,
there is a problem understanding the ICS fully...
I want to use an MC9S08QG8 with a 16 MHz crystal, resulting in 8 MHz Bus clock. I need a fast running and accurately clocked application.
The MC9S08QG8 Data Sheet appears quite detailed but doesn't contain hints, which ICS mode is best suited for my needs. So I describe what I want to use and kindly ask for confirmation or improvements (or hints for the right literature).

The mode I would choose is "FLL Bypassed External (FBE)", but I cannot find any configuration with the "processor expert" software without any warning.
Essetially I cannot divide the external clock sufficiently (needed: /512, max. possible: /128) such that the FLL/filter input is in the range of 31.25 kHz to 39.0625 kHz.

I cannot find any statement, that the FLL must be feeded with such a low frequency. Ok, if I do not meet the condition, I cannot rely on DCOOUT and ICSLCLK. But does it do any harm, will any circuitry be damaged?
Can I use ICSC2=0x36 and, after waiting on OSC Initialization, ICSC1=0xb8?
All peripherals may be clocked with the BUS clock (8 MHz):
TPM, MTIM can be divided down sufficiently, ADC, IIC and SCI are said to work perfectly, BDM runs with 8 MHz - compatible with SpYder. The only question, provocated by warnings in the MC9S08QG8 Data Sheet and the "Processor Expert": What goes wrong when the range of 31.25 kHz to 39.0625 kHz for the FLL isn't met?

I would have appreciated some recommendations in the MC9S08QG8 Data Sheet, which ICS-mode is best suited for which needs; chapters 10.4.1.1 to 10.4.1.6 would be an ideal place for this - or does any other document exist which contains such information? An application note?

Thank you very much in advance for your help.
Kind regards,
Helmut

P.S.: I have searched...   

Added p/n to subject.

Message Edited by NLFSJ on 2009-02-11 09:22 AM

[bigmac]

Hello Helmut,

To use a 16MHz crystal, you will need to use FBELP mode.  With the LP bit set to 1, the FLL will be disabled so it should not matter that the reference frequency to the FLL is out of range.

The sequence of events is described in paragraph 10.5.1.1.  Ultimately, you might have the register values ICSC1 = 0x80, ICSC2 = 0x3C.

Another possibility would seem to be to run the FLL from the trimmed internal reference (IREFS = 1), but to select the external crystal as the bus clock source (CLKS = 10).  But this does not seem to be documented, so may not work as intended.

Regards,
Mac

[Helmut]

Hello Mac,
thank you for your quick response.

Yes, FBELP looks perfect, but... "The ICSLCLK will be not be available for BDC communications." (10.4.1.6).
ICSLCLK is the default clock for BDC in most cases (except when the controller is in "Active BDM" during reset, 17.4.1.1).
I can't follow the many abbreviations and advices concerning the reset/clock-machinery of the BDC and simply do not know which clock is in effect when I just simply download and debug my program and if SpYder can deal with this.

Ok, I switch BDC to Bus clock, but I can't - it must be done by the debug adaptor (SpYder). And there is no information if SpYder can or will do this.

The next step will be to try it out and to report the result here (I'm slow, scrupulous and have not enough time, it will take a while... :smileyhappy:.
...and of course to ask the SofTec Microsystems engineers, but they whiped SpYder out of their portfilio.
If it doesn't work I can try IREFS=1 & CLKS=10.
If somebody already knows that it will or won't work (16 MHz, FBELP together with USBSPYDER08) please drop a note.

Again, thank you very much for your help.
Kind regards,
Helmut