With further investigation, it seems that the IAAS interrupt occurs because the 2 MSBs of the 10-bit slave address are the same for both slaves connected on the bus. Hence, the first byte transmitted by the master is received and acknowledged by all slaves having the same 2 MSBs as transmitted by the master, causing the IAAS interrupt to occur for both slaves..it seems. Thankfully, only the slave with the address matching the second address byte (the remaining 8 bits of address) sent by the master responds with the 2nd ACK and the transaction continues as normal.
This behavior is not describe in the QE128 Reference Manual. And yes, I RTFM for those of you who wonder.
Any chance of someone experiencing the same problem/behavior?