Handling multiple ADC channels in MC9S08AC128

[adc]

Hello

 I am new to this controller.

 In adc i needto use 14 channels.

please suggest which trigger is best in concern with speed either software trigger and hardware trigger.

About continous conversion need more information.

how to calculate the sample time with adc clk is equal to 8Khz

please guide me dont feel bad since i am asking basic questions.....

Thanks for replies  

[bigmac]

Hello, and welcome to the forum.

Since you need to monitor 14 channels, you would likely need to initiate each conversion via software.  The value sent to the ADCSC1 register will select the channel for the conversion, and then initiate the (first) conversion.  To monitor a different channel will require a new value to be written.

When continuous conversion mode is selected, at the completion of a conversion, a new conversion will immediately start (on the same channel).  This mode would again appear inappropriate to the monitoring of 14 different channels.

An ADC clock rate of 8kHz is far too low.  From the datasheet, the allowable minimum rate is 400kHz.  For the ADC conversion time, it is possible you may need to reference the datasheet for the 'AC60, where the information may be found within Table 9-11.

Regards,

Mac

[adc]

Hello sir,

            Thanks for reply.

            actually which type of interrupt method is preferrable either software or hardware trigger.

            If one adc channel the input wave i need sample it for 256 times and calculate the true RMS of that wave from the 256 digital values.

            All other channels simply read the digital data from particular channels.

           so selecting clock for adc as well as the chip please guide me sir

           Thanks fro replies

[bigmac]

Hello,

The approach used may depend on the timing requirements for the readings, particularly the frequency range applicable to the AC RMS measurement.  At the lowest measurement frequency the 256 readings should represent at least one cycle of the voltage waveform.  This may well dictate that a timer be used to initiate each of these readings at a periodic interval.

The hardware trigger utilises the RTI, and this requires either an external clock, or the use of the 1Hz clock which may not be suitable for this application.

The use of a TPM channel may give more flexibility.  Each new reading would be initiated within the channel ISR.

If the RMS signal frequency is relatively low, there may be sufficient time to intersperse one of the other thirteen channel readings between each of the AC readings.  These readings could be initiated within the ADC ISR.  You may also need to consider whether any of the other thirteen channels needs to be subject to either averaging or filtering of multiple readings, in order to reduce fluctuations due to noise.

Regards,

Mac 

[adc]

Hello Mac sir,

                  Thanks for the reply still i didn't get the clock information for ADC.

                  But i got doubt how short sample and long sample will work?

                   and reading in datasheet,in section 8.54.2 completing conversions

                   described about blocking i got struck how to enable or disable the block for data read?

                 please clarify doubts regarding above mention topics

   Thanks for replies

[bigmac]

Hello,

Your datasheet reference is not clear.  I was using the datasheet for the 'AC60 device.  Here, section 9 covers the ADC module, and there is no sub-section 54.  I wonder if the following is what you might be alluding?

9.4.3 Data Result High Register (ADCRH)

ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured for 8-bit conversions both ADR8 and ADR9 are equal to zero. ADCRH is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. In 10-bit MODE, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, then the intermediate conversion result will be lost. In 8-bit mode there is no interlocking with ADCRL. In the case that the MODE bits are changed, any data in ADCRH becomes invalid.

 If you are using 10-bit mode, this means that ADCRH is read prior to ADCRL.  You will need to be a little more specific about the problems that you perceive.  Perhaps you might post your ADC code if you are not obtaining the results that you expect.

Regards,

Mac

[adc]

Hello sir

            I am referring to datasheet AC128.

            sir please send any adc code to Support @ smartb.net

            for my reference for clock selection for adc and as well as for functioning of chip.

Thanks for replies

Geetha