HCS08ac60 TPM output compare

[BobMac]

Hi Guys;
 I've been blindly adding a new compare value to the channel 0 VL and VH after an output compare in my ISR. Outside of getting this to work, what happens during the comparator going true (match) and generating the compare match interrupt?
 Am I adding a new value to the previous value over and over or is the previous comp value cleared and a new one needed for the next compare or what?
 I can't find any explanation in the documentation and can't get this little nagging question out of my mind.
 Kinda like "it's a small world after all" theme. Last time at Disneyland after taking the kids on this ride, this stooped mind numbing jingle stayed in my mind for a week! Ooo the pain.
Best regards, BobMac  
 

[peg]

Hi Bob,

I am not sure if I understood you correctly (maybe its that jingle playing in the background) but here goes...
The counter just keeps on counting regardless of whether or not a compare has occurred, it never stops unless you deliberately stop it. If you just reset the compare flag but don't update the compare register it will fire again at the same count next time through. If you take too long to update the register with a value a small time ahead of the last you will get your interrupt not in a short time but in approximately 1 counter modulo time.
Did that put your mind at rest?

[BobMac]

Hey, Hi there Peg!
 The sequence would be then;
1) compare function goes true and the compare IRQ is generated
2) the new compare value is added to the previous value by my ISR and the compare cycle
   continues again.
3) the next compare goes true when the new compare value plus the previous compare value is reached.
   As long as I keep adding the new compare value to the previous one this cycle will continue
   or am I completely missing the point?

Thanks for your time! Bob

[bigmac]

Hello Bob,

Perhaps the terminology need to be clarified a little.

1. An output compare condition (interrupt) will occur when the timer count value equals the channel register value.
2. It is then usual to add (16-bit modulo) an increment value to the current channel register value, and load this new value to the channel register.
3. The next output compare condition will occur when the counter value equals the new channel register value.  The period between the two interrupts will correspond to the increment value.

This process can be repeated to obtain repeated output compare interrupts on a regular basis.

Regards,
Mac