HCS08SG16/32 internal clock setting / divider problem

[ttom]

Hello,

I am new to this forum and have a question to the internal clock and I hope, someone can help me.

First, my environment:

Codewarrior 6.2.2

Demoboard DEMO9S08SH32/SG32

What I want:

I want a CPU - clock of 4 MHz

What I did:

setting ICSC1 to 0x06

(clock source = FLL, Reference divider = 000, Internal reference select = 1, internal refence clock enable = 1, internal reference Stop Enable = 0)

setting ICSC2 to 0xC0

(Bus frequency divider = 11 -> divide by 8)

my calculation for this setting:

the FLL multiplies the 31.25 kHz by 1024, so I get a internal fequency of 32 MHz, then divide by 8 -> so I have 4 MHz.

(according to the datasheet in the system clock distribution diagram the cpu is connected to ICSOUT and not to BUSCLK)

I checked the cpu frequency in the following way:

I toggle a port:

    asm BSET 5, 0x02
    asm BCLR 5, 0x02
    asm BSET 5, 0x02
    asm BCLR 5, 0x02
    asm BSET 5, 0x02
    asm BCLR 5, 0x02

And then I measure the time between 2 rising edges. The BSET and BCLR instruction takes 5 cycles each.  I measured a time of 5 us (for the 10 cycles between 2 rising edges). So I have a cpu clock of 2 MHz (0,5 us Periode).

Does anybody know, where the additional divide by 2 comes from? I assumed a clock of 4 MHz.

have a nice evening,

Thomas

// select internal reference
// activate ICSIRCLK (internal reference Clock enable)
  ICSC1 = 0x06;

// Bus frequency divider = 1

  ICSC2 = 0xC0;

I tried to check the cpu clock.

I use the internal reference and the FLL, so I ge

[tonyp]

From the reference:

ICSOUT — This clock source is used as the CPU clock and is divided by two to generate the
peripheral bus clock, BUSCLK

Did you account for that?  The bus clock divider acts on the already divided-by-two ICSOUT.

[ttom]

Hello,

as far as I understand the System Clock Distribution Diagram (Figure 1-2 on page 22 of the MC9S08SG32 Data Sheet, Rev 6), the CPU is connected directly to the ICSOUT. All the other periphal parts are connected to the BUSCLK, which is ICSOUT / 2.

I use the internal clock and the FLL, according to the Figure 11-2 Internal Clock Source (ICS) Block Diagram (on page 172 of the datasheet), the ICSOUT is the output of the FLL in my setup, with a divider by 8 (BDIV = 11 Encoding 3).

So I assume a ICSOUT of 31,25 kHz * 1024  =32 MHz / 8 = 4 MHz and a BUSCLK of 2 MHz.

Are the output pins driven not by the cpu but by a another block, wich is connected to the BUSCLK? 

[tonyp]

I think you have a misunderstanding.  CPU clock is divided by two (or more depending on BDIV) to get the bus clock.

All CPU instruction cycles refer to the bus clock.  That should make it clearer.

Message Edited by tonyp on 2009-10-28 05:27 PM

[ttom]

Hello tonyp,

thank you for your answer.

I assumed, that the CPU clock is directly connected to the ICSOUT (as in the clock distribution diagram). If you are sure, that the cpu is connected to the busclock (which is ISCOUT / 2), then my calculation is correct and I have to add the /2.

Many thanks

Thomas 

[tonyp]

Again, the CPU is connected to ICSOUT, but the bus clock is CPU clock (or ICSOUT) divided by two.  All cycles are in relation to the bus clock.  Don't confuse CPU clock and bus (or instruction cycle) clock.

[ttom]

Hello,

thank you again for your response.

Sorry, I think I am a little bit confused. My problem in understanding is the following:

You say, that all instruction cycles are in relation to the bus clock, which is ICSOUT / 2.

I verfied it by measure with the oszilloskope. And I see, you are right.

But in the datasheet, there is only 1 connection from the ICSOUT to the CPU.

What I want to know is, how I can estimate the duration of a certain function when I count the cycles in the simulator. Are this cycles  ICSOUT cycles or ICSOUT / 2 cycles?

I had a look at the datasheet, again. At the instruction set summary, there is a column with execution cycles - described as "internal bus clock cycles".

So the CPU seems to run with the bus cylce, which is ISCOUT / 2.

Are there any commands of the CPU which run with "full speed" ICSOUT - clock and not the BUSCLK?

I am sorry for the silly questions, this is my first time using freescale. 

[tonyp]

I think the quoted text shows your confusion.

The CPU clock is not the clock at which instructions are executed.   So, the CPU does run with the ICSOUT.

BUT, the execution of instructions is done not at the CPU clock but at the BUSCLK, which at its fastest is always half the CPU clock.

No, there are no instructions that run at ICSOUT/CPU clock.  All instructions run at BUSCLK which is the maximum clock you can achieve (full speed, when BDIV is 0 - divide by 1).

---

ttom wrote:

        So the CPU seems to run with the bus cylce, which is ISCOUT / 2.

Are there any commands of the CPU which run with "full speed" ICSOUT - clock and not the BUSCLK?

---

Message Edited by tonyp on 2009-10-29 10:28 AM

[ttom]

Hello tonyp,

thank you very much for your helping hand.

I see that the instructions are executed by the BUSCLK (this is what I have also find out by the oszilloskope).

You wrote, that the CPU runs with the ICSOUT (as shown in the datasheet). I don't understand at this point, what the cpu is doing with ICSOUT - clock, when all instructions are done with the BUSCLK. What is the CPU doing except executing instructions?

Sorry for this maybe silly question - but I try to understand the Freescales.(my first CISC microcontroller, I have worked with RISC up to now).

Thomas

[tonyp · Accepted solution]

Just look at it this way:

The 9S08 CPU needs two clock times to generate a single instruction clock.  (For comparison, the older HC08 and the HC11 needed four.)   That's just how the chip hardware is designed.  For example, when they tell you to use a maximum 50MHz crystal, this translates to maximum 25MHz execution of instructions.

Message Edited by tonyp on 2009-10-29 01:51 PM

[ttom]

Hello tonyp,

many thanks for your explanation and opening my eyes :smileyhappy:

I see, that the CISC processors are quite slow for easy I/O instructions (e.g. setting a bit in a output).

with the freescale HCS08SG32 setting one output @ 32 MHz ICSOUT:

instruction BSET = 5 instruction cycles = 10 ICSOUT - cycles = 0,31 us

with eg. ATMEL AVR (RISC architecture) the set Bit operation for a I/O port lasts @ 8 MHz:

instruction SBI = 2 cycles = 0,25 us

I am very glad that you helped me.

Many thanks,

Thomas