HC9S08QG + PE Cyclone = sync error!

[irob]

Hello, I'm trying to fire up some new hardware. This is my first project with an S family Freescale part. It's the HC9S08QG8CFFE, QFN16. I've had several successful HC908QT projects using the MON08; this is my first board to be programmed with the background debug mode port.

Well, it's not working with my P&E Micro Cyclone Pro and the BDM cable I made.

I've triple checked the wiring of the BDM cable to my target. I have verified connection from the Cyclone to the target MCU through the cable. On my scope, I can watch the background pin and reset pin both go low and then release during an attempted communication from the Cyclone. Oh, and I have good power on the board too, kinda high but within specs, +3.4V

The Cyclone setup is this:

Cyclone PRO USB port
Interface detected: Yes
Fimware Version: 6.76 (latest)
Target CPU Info CPU: HCS08 Processor - Autodetect
MCU reset line: High
Reset delay - both checked, set to 2000ms to allow plenty of time
Cyclone Pro Power Relay Control - both checked, 5V, 2000ms up/down

reports this error:
sync returned no result

What does that mean other than a bad communication?

I've cranked up the delays really high thinking that the rise time was too slow on this target. I've used the BDM connection guide as outlined in the 9S08QGx datasheet which recommends a 4.7-10K pullup and a 0.1uF pull down.

Any ideas?

Message Edited by irob on 03-24-200604:49 PM

[irob]

I've looked further into my situation. I've got a scope on both Reset and Background while my Cyclone Pro initiates communication. I'm using an external bench power supply to monitor power consumption; thus I'm using the relay power control.

I see the Reset and Background pulled high, then the power cycles properly through the relays, and then the RST/BKGD toggle low simultaneously during the power cycle. After that, nothing happens with either line.

I even disconnected the BDM cable from my target, scoped right on the BKGD/RST pins with an external pullup on each. Nothing is happening. It appears that my BDM interface is not initiating the cycle.

Thoughts?

[irob]

Hmmm, in the interest of getting this working by Monday (gulp!!), I tried to use my DEMO9S08 board as a BDM programmer, per this old thread on FreeGeeks.

Although I wasn't sure how to handle the cycling of power that the target needs (right?). So far, this method hasn't worked either, but I have much better results.

For one, I can finally now see some activity on the BKGD/RST pins during the attempted program cycle. World's improvement over my Cyclone!

Yet, I get the same error: "SYNC returned no result" after trying to set the frequency, "Frequency change to ~0hz." Not sure what that last part's about. I suspect that the BDM can't read the target's internal clock, which should be starting out of reset.

And I get these same results for all 10 of my newly built targets. This has to be something fundamental with either the target boards or my BDM cable. And I've checked the cable 100 times already.

[irob]

Well, I've now got one of my targets finally talking to the P&E programmer, progHCS08.exe, v1.37. You know what made it work?

Had to short the reset pin of the processor to +Vdd. The pullup I have on that pin is not enough.

The trouble is, I can't repeat this on my other targets. The fix is only working on the one target. Sounds like a marginal problem, huh?

Anyone have any ideas on this? The BDM interface should be the simplest part of the design!

[irob]

Ok folks, I've gotten this solved with much help from Freescale factory and local FAEs.

The quick answer:
1) Set a BKGD pullup to 3.3K Ohms. This pullup is not mentioned anywhere in the Freescale literature. It was taken from the DEMO board schematics by Axiom.
2) Set a RESET pullup to 2.2K Ohms. The DEMO board doesn't have this pullup, but I found that I needed something stiffer than the internal MCU pullup.
3) Set the ICD Connection Assistant (if using CodeWarrior's debugger) or the Connection Manager (if using one of the standalone P&E Micro programmers) check box labeled "When initiation a debugger reset, the MCU Reset Pin should be used (else use a debug module reset)".

From my observations, the BDM interface is very sensitive. Literally, 10K Ohms on either RESET or BKGD would prohibit communications to my target boards. This was also found to be true with even the DIP 9S08QG8 chip that ships with the DEMO board. I pulled it off the DEMO board, inserted it into a breadboard and attempted to communicate with it using either the P&E BDM Multilink cable or the BDM header on the DEMO board.

Neither of those programming methods worked with higher pullups. Instead, they had to be lowered. In addition, I had to be consistent about power cycling my target boards once after initial communication attempts.

Message Edited by irob on 04-06-200612:14 PM

Message Edited by irob on 04-06-200612:24 PM

[k5jhf]

Thank you very much for your Help, I will try this as soon as I get my chips back. I loaned them to another engineer to try to solve this problem. I was so frustrated :smileyhappy: Thank you for your work and Freescale should be ashamed. Thank you again for your perserverance :smileyhappy:

Regards,
John

[peg]

Hi Rob,

I note my Axiom GB demo board has 10k PU on Reset and 4k7 on BKGD.

4k7 is pretty stiff considering "no external pullup is required" (quote from manual)

Having said that I was silly enough to read the data sheet and have designed a GT32 PCB with no PU's on the BDM port. I have commissioned 10 boards so far with no programming issues and have just ordered 50 more PCB's.

I'll let you know how these go.

BR Peg