Hello, and welcome to the forum.
The internal oscillator that you refer is the DCO (digitally controlled oscillator), which is part of the FLL (frequency locked loop) that may be utilized to generate the bus clock. The DCO has a control range of 32-40 MHz. The DCO frequency will be divided down to a lower frequency, to provide the bus frequency (20 MHz maximum). The minimum division factor is 2. The division factor may be increased above this using the BDIV setting.
An internal reference oscillator is provided to control of the FLL frequency. This has a trimmable frequency range 31.25 - 39.0625 kHz. The FLL will lock at a frequency of 1024 times the internal reference frequency (32 - 40 MHz). The FLL will provide the bus frequency using the internal reference, whenever FEI mode is selected. This is actually the power-up default mode.
Before trimming is applied, the internal reference frequency will be within the approximate range 35kHz +/- 25%, and the default BDIV setting will give a total division factor of 4. The resulting bus frequency will be about 9 MHz +/- 25%. The trim value needs to be calibrated for each individual device, to achieve a specific reference frequency. This calibration is particularly important if you need to operate close to the maximum allowable bus frequency.
To achieve 20MHz bus frequency, using FEI mode, the following steps would be required -
- During the flash programming process, the internal reference needs to be calibrated for a frequency of 39.0625 kHz. This is the "non-volatile (NV) trim", and is programmed to a specific flash memory location.
- During MCU initialisation, the NV trim setting is read from flash, and written to the normal trim register. The bus frequency will now be close to 10 MHz.
- Now change the BDIV setting from power-up default, to increase the bus frequency to 20 MHz. This should never be done until after the interal reference frequency has been trimmed.
Regards,
Mac