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Robinwithu
Senior Contributor I

Hello Ankur Gandhi Arpita Agarwal

 

I am having a question Regarding the stabilization of  internal Oscillator for MC9S08RN8 MCU.

 

I using using internal FEI mode and the default Bus frequency is 10Mhz and i am doing the changes in the ICS register to get 20Mhz.I would like to know that should i have to wait for certain amount of  time after changing the ICS  register till the Oscillator is stable (Internal Reference frequency and FLL)  or MCU take care of itself and than it will execute the Rest of the code . please correct me if  i am wrong , it will take maximum 1.3msec  (300µsec for Internal reference clock and 1 msec for FLL)maximum time to generate stabilize clock.

 

 

Thank you n Kind Regards,

Robin

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arpitaagarwal-b
NXP Employee
NXP Employee

Hello Robin,

If you are changing only BDIV, then polling of LOCK is not required as FLL clock will not be changed.

It is only bus frequency divider.

If this post helps you, kindly mark it as correct/helpful answer.

-Arpita

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Robinwithu
Senior Contributor I

Hi iansmusical

Thanks for reply. Actually i just found one problem , in while loop when i am comparing while (ICS_S_LOCK==0){;}, so in this case After stabilization of internal oscillator LOCK bit will set to 1 which means in assembly code it should be (BNE) branch if not equal but it's giving me BEQ in assembly code .why i don't know? or am I understanding  it wrong?

I am expecting that it should leave the while loop (After making sure that FLL is locked) but it doesn't.

BEQ= branch if equal

BNE= branch if not equal

Thanks and Kind Regards,

Robin

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iansmusical
Contributor V

Hi Robin,

Yes your assumption is correct that the while loop will exit when the lock bit is set to 1 because you are saying while ICS_S_LOCK is equal to 0 loop and check again.

The resultant assembler is also correct in using BEQ because you are saying branch or check again if ICS_S_LOCK is still equal to 0. When ICS_S_LOCK becomes 1 the BEQ condition will not be met as the "== 0" part is no longer fulfilled.

Thanks,

Ian

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Robinwithu
Senior Contributor I

Hi Ian,

Actually i debug the code and found that LOCK bit is = 1, which means that the code should leave the while loop but when i am flashing the code in MCU it doesn't go further and as soon as i changed the while(ICS_S_LOCK==1) it work fine , that's why i am wondering , is it BEQ  correct or it should be BNE? cause BEQ says that Branch if Equal , for my understanding if the condition is matched than do the branching or exit the loop. isn't it so? n in my case it should exit the loop only in case when the condition is false.

Thanks n Kind Regards,

Robin

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iansmusical
Contributor V

Hi Robin,

I don't think there is an issue with the assembler that is generated for either:

     while(ICS_S_LOCK==0);

     while(ICS_S_LOCK==1);

It sounds more like for some reason the lock isn't occurring in standalone mode but it is when debugging. As Arpita said in debugging mode the clock is required to be stable before debugging can take place and therefore the lock bit will be set to 1.

I think you're probably best trying to find out why the lock bit remains 0 in standalone mode. Then you can use the first while statement above to signify that the lock has been obtained.

I'm not sure if this applies or not but the while loop might be better as:

     while(ICS_S_LOCK==0) {

          nop;

     };

Can someone confirm whether the "nop" is required?

Thanks,

Ian

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Robinwithu
Senior Contributor I

Hello iansmusical,

The above problem of FLL locking  is solved , the problem was WDT, it has always reset the MCU after appx. 9 msec , so that before the Oscillator stabilize the MCU get Reset.Actually what wondering me is that in Datasheet the max. Stabilization time for FLL is 2 msec but in oscilloscope i have seen it took around 21 mSec , n that was the reason why it was never stabilized and get Reset cause of WDT.

can you give me Some suggestions please, why it's taking 21 msec or am i doing something again wrong?

Here is that Actual code :

#include <hidef.h> /* for EnableInterrupts macro */

#include "derivative.h" /* include peripheral declarations */

  volatile byte NV_FTRIM_INIT  @0x0000FF6E  ;  // LSB     ICS_C4

  volatile byte NV_ICSTRM_INIT @0x0000FF6F  ;  // MSB     ICS_C3       

    // Main Programm is working at 20Mhz = 512 * 39062.5 = 20Mhz    =>    39062.5 is a Default Factory Trimmed frequency  in ICS_C3 & ICS_C4 Registers

    void main(void)

   

    {

       

          

        

         DisableInterrupts;

        

        

         WDOG_CNT = 0xC520;                           // write 0xC520 to the 1st unlock word

         WDOG_CNT = 0xD928;                           // write 0xD928 to the 2nd unlock word

         //Disable Watchdog

         WDOG_CS1 = 0;                                // disable Watchdog

         WDOG_CS2 = 0;

         WDOG_TOVAL = 0xFFFF;

         WDOG_WIN = 0x0000;

        

      

        if ( NV_ICSTRM_INIT != 0xFFU) {                                              // 0xFF6FU  Test if the device trim value is stored on the specified address

           

            ICS_C3    =  NV_ICSTRM_INIT ;                                            // This Registers are not Define in Derivative.h file thats why we have to define this Environment Variable before the start of code

            ICS_C4    = ((NV_FTRIM_INIT)  & 0x01U);                                    // Trim the internal clock  :((NV_FTRIM_INIT) & 0x01U);

           

          }

       

       

          ICS_C1 = 0x04;                                                                 // internal reference clock to FLL and FLL is generating 16000-20000 Khz  ; Ref. Freqeuncy  is set at 31250-39250 Hz * 512 = Appx.16-20 Mhz

          ICS_C2 = 0x00;                                                                // BDIV = 00, Freq is now 16-20Mhz   

       

          PORT_PTAOE = 0x0F;

          PORT_PTAD_PTAD2 = 0;

     

          while (ICS_S_LOCK==0)                                             // wait till  FLL is  locked.

          {

            PORT_PTAD_PTAD2 = 1;

    

          }                                                                        

                                                                                                                          

          PORT_PTAD_PTAD1=0;                                              // Initialize PORTA1 pin

          while (1)

                        { PORT_PTAD_PTAD1 = 1;

                          PORT_PTAD_PTAD2 = 0; }                         // Set PORTA1 pin in forever loop

       

       }

Thanks and Kind Regards,

Robin

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iansmusical
Contributor V

Hi Robin,

Great! I'm pleased to hear you've solved the issue but why the FLL is taking 21ms to lock is a mystery! What trim frequency are you using? Are your two trim values plausible? As soon as you write the trim values the FLL will re-acquire its lock, so I wonder if it's worth checking the lock before you write to the BDIV registers (just to avoid any out of range clock frequency)?

Guessing a little I wonder if a noisy power supply could effect the chip. Do you have decoupling capacitors etc? Do you have another RN8 that you could try the code on to see if the current chip is out of spec?

Thanks,

Ian

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Robinwithu
Senior Contributor I

Hi Ian,

Thanks for reply. Actually i tried also without BDIV and i got the same result.Actually i am using Default trim values , as you can see in the below code and which is 39062.5 hz.

I tried on S08RN4 and RN8 on my project PCB and also on my own made tryout PCB but i am getting everywhere same result of 21 m sec  stabilization time.

        if ( NV_ICSTRM_INIT != 0xFFU) {                                              // 0xFF6FU  Test if the device trim value is stored on the specified address

          

            ICS_C3    =  NV_ICSTRM_INIT ;                                            // This Registers are not Define in Derivative.h file thats why we have to define this Environment Variable before the start of code

            ICS_C4    = ((NV_FTRIM_INIT)  & 0x01U);                                    // Trim the internal clock  :((NV_FTRIM_INIT) & 0x01U);

          

          }

I am using a voltage regulator for the MCU  power supply and which is Automotive Certified.

I thought may be cause of POR reset it takes more time , instant of disabling the WDT, i increased the WDT timeout around 100 msec and even in WDT Reset the Stabilization time is 21 m sec.(Wondering ........... :smileysad:)

can you suggest me some tips to check noisy power supply ?

I do have Following bypass capacitors

1) Between Power supply and GND = 1nF || 100 nF || 1 µF all are in Parallel.  1µF is at the Output of Voltage regulator and the Rest two are near to MCU Power supply pin .

Thanks and Kind Regards,

Robin

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iansmusical
Contributor V

Hi Robin,

Hmm... you'd expect the default trim values to work! Have you tried 31.250KHz to see if that makes a difference to the lock time? If you're using an automotive certified power supply then there shouldn't be any noise or much ripple etc. Plus you've got all the capacitors I'd have suggested.

I note in the data sheet that it says the lock time is "characterised" and not tested on each chip but surely it wouldn't take 21ms!!

Thanks,

Ian

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Robinwithu
Senior Contributor I

Hi iansmusical,

I tried with 31250Hz and the Stabilization time increased from 21msec to ca.26.5 msec .

Thanks and kind Regards,

Robin

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iansmusical
Contributor V

Hi Robin,

Hmm... that's even worse! I can't imagine that all S08 devices take this long to get the lock but I've never measured it either. Do you have any other non RN devices you could try it on?

What you really need now is some comment from Freescale on this... :smileygrin:

Thanks,

Ian

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Robinwithu
Senior Contributor I

Hi Ian,

Thanks for reply ...you are right ....but as usual  they are always busy :smileywink:.let's hope they will see this and reply :smileygrin:.

i notice one thing as i change the Internal reference Freq. example 31250,32768,39062.5 for each freq. i am getting different stabilization timing :smileyshocked:.

Thanks n Regards,

Robin

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Robinwithu
Senior Contributor I

Hi Ian,

Thanks for suggestion and your kind reply ... i will test it with 31250Hz trim value and will let you know the result.

Kind Regards,

Robin

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Robinwithu
Senior Contributor I

Hi iansmusical,

I tried as you said above with "NOP" in while loop but the result remains same. :smileysad:

Thanks n Kind Regards,

ROBIN

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arpitaagarwal-b
NXP Employee
NXP Employee

Hello Robin,

You will have to wait till the clock will be stable.

For that, you need to poll LOCK flag in ICS_S register. It will set when the clock will be stable.

See the description:

Lock Status

Indicates whether the FLL has acquired lock. Lock detection is disabled when FLL is disabled. If the lock status bit is set then changing the value of any of the following bits IREFS, RDIV[2:0], or, if in FEI or FBI modes, TRIM[7:0] will cause the lock status bit to clear and stay cleared until the FLL has reacquired lock.

If this post helps you, kindly mark it as correct/helpful answer.

-Arpita

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Robinwithu
Senior Contributor I

Hi iansmusical,

please can you help me with this topic.

Thanks and Regards,

Robin

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iansmusical
Contributor V

Hi Robin,

I'm not sure if I can be much help but changing the BDIV can be done at any time and doesn't effect the FLL lock. Looking at the RN reference manual section 7.6.5 I see that changing the TRIM register will cause the lock status to be cleared until the FLL has reacquired the lock.

Guessing I'd have thought the lock would be obtained in standalone or debug mode because the internal clock is the default and must be locked to function!?

Thanks,

Ian

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Robinwithu
Senior Contributor I

Hi Ian,

Thanks for reply , yes BDIV doesn't have any effect and I am trimming it default value so their is no change in trim register.Try to find out myself what i am doing wrong.

Thanks and Kind Regards,

Robin

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Robinwithu
Senior Contributor I

Hello arpitaagarwal-b37570,

In debugging mode the Default value of ICS_S=0x50 instant of 0X10; before doing any kind of debugging. is that correct ? or may be it's has already stabilized the Internal oscillator and that's why i am getting the FLL locked. or should i get the FLL locked after writing the default trim value and changes in BDIV reg.

Thanks and Kind Regards,

Robin

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arpitaagarwal-b
NXP Employee
NXP Employee

Hello Robin,

In debugging mode, LOCK status bit will be set only as it has crossed the chip start-up phase. And also, debugging can be performed after clock stabilization only.

So this observation is correct. As discussed earlier, changing BDIV should not change the lock status. In FEI mode, changing trim value will unlock the oscillator.

If this post helps you, kindly mark it as correct/helpful answer.

-Arpita

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Robinwithu
Senior Contributor I

Hi Arpita,

Thanks for reply , please can you tell me than why code hanged here  " While (ICS_S_LOCK==0) " as soon as i changed it to "While (ICS_S_LOCK==1)" the code work normal. but as we know that LOCK polling like this [  While (ICS_S_LOCK==1) ] is not correct.



Thanks and Kind Regards,

Robin

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