DV16 TPM Question

[dwhansel]

Hello, I seem to have an issue successfully writing to the modulo register on my 9s08dv16 MCU.  I am quite puzzled, here is what it is doing:

c -source

TPM2CNT = 0;    
TPM2MOD = 0x0460; /* 280uS @ 0.25uS/bit */
TPM2SC_TOIE = 1; /* enable the modulus interrupt */

assembly

CLRH

STHX  _TPM2CNT.Word

LDHX  #0x0460

STHX  _TPM2MOD.Word

As I step through this code, the TPM2 modulo register at address 0x63-0x64 remains at zero.  HX is being properly loaded with 0x0460, the STHX command appears to be executed, but the reported memory location doesn't change.  I can set the location directly using the PE micro multilink debugger interface with CW 6.3 debugger and it works fine.  It behaves the same regardless of debugger attached or not(verified with o-scope).  It also behaves the same if I break the write into high byte and low byte.  Also, I don't completely understand the coherency mechanism so I wrote a value that was a couple of timer ticks higher then the current timer value to see if the location would update when TPM2CNT == TPM2MOD-1, no effect.

any ideas?

thanks

Doug

[dwhansel]

Further investigation has revealed writing to the TPM status and control clock select bits(TPM2SC_CLKSx), prior to writing to the TPM Modulo register (TPM2MOD) prevents writing to the modulo register.  The behavior is repeatable on TPM1 and TPM2 on at least two different DV16 MCU test subjects.  Writing to the modulo register first causes the write to be accepted.

If anybody reading this has any ideas or could re-create, I would greatly appreciate it.  I assume there is some coherency lockout or poorly documented order of events issue catching me here.

One thing I have tried is resetting the overflow bit (TOF) prior to writing the modulo register, still no good.

on a serious deadline, any advice would be great.

Doug

[bigmac · Accepted solution]

Hello Doug,

Yes, there is a coherency mechanism for updating the 16-bit registers within the TPM module, including TPMxMOD.  The channel registers are also affected, and unfortunately there are signiffican coherency mechanism differences between V1, V2 and V3 modules.  The following post addresses update of channel registers for V3 modules, and may be of general interest.

https://community.freescale.com/message/62954#62954

To achieve immediate update of the TPMxMOD setting, I suggest this should be done with the TPMxSC_CLKS setting at 00 (clock disabled).  Update should then occur when the second byte is written, and will be independent of the prescale setting.  Otherwise, the update would be delayed until the next TPM clock edge, from the prescaler.  Within this period, it is possible for other TPM register writes to clear the coherency mechanism, so the value never gets updated.

Another possibility is to test and wait for the updated value before any other TPM register writes.

Regards,

Mac

[dwhansel]

Thanks Mac, zeroing the CLKS priort to writing the MOD register worked for me.  I am still not sure what advantage this design "feature" provides, but I can work around it now.

Doug