Capacitance on output pins?

[DSbob]

How much is tolerable?  Specifically, our product just reaching volume production uses a 9S08QG (again) and has a yield problem.  The controller with that uC plugs into a somewhat specialized remote control SMPS, and transmits blinky light signals via SPI to 75HC595s on a control panel.  We risked a couple feet (0.7m) ribbon cable for this and a couple other non-critical functions.

On a very few units over a fairly narrow range of SMPS operation, the blinky lights go crazy.  SMPS replacement eliminates the symptom.  I finally got around to characterizing a bad unit - 20 MHz chirps at the presumed SMPS PWM transitions, growing big enough to upset 3V3 logic as symptoms occur.

Tried some ferrite ribbon cable clamps suggested by the SMPS vendor, supposed to be ~30 ohms at 20 MHz.  No effect.

In desperation and with assumptions of 100 ohm pin impedance and 1 MHz OK for a cutoff frequency, we hung 1nF caps between the SPI signals and ground.  Symptom eliminated, and the signal transitions are still 2x-3x faster than the recommended '595 maximum (specified at 2V and 4.5V).  We have uC pins set to slow transitions & low drive (after seeing overshoot with opposite settings, trying to diagnose this earlier) so could probably reverse that if faster transitions were needed.

This might violate the uC absolute maximum instantaneous output current rating, not by much nor for very long.  I wonder what other trouble it could get us into?

Of course I'm seeking support from the SMPS maker toward a fix on that end.  Just thought I would ask for advice from the forum before going to the trouble of a board spin...

[bigmac]

Hello,

You do not say whether the MCU is the SPI master or slave?  Either way, you will not achieve a SPI clock frequency of 20 MHz.  The maximum limits for a 'QG8 device will be fbus/2 for SPI master, and fbus/4 for SPI slave.  If you are operating at the maximum bus frequency of 10MHz, this will give 5MHz maximum for a master, and 2.5MHz for a slave.  For a lower bus frequency, the upper limits will be correspondingly lower.

At very high clock frequencies, transmission line considerations may come into play, with the need to terminate each end with a "characteristic impedance" value, to eliminate signal reflections.  However, this is not generally feasible with low power devices due to insufficient drive current being available.  And I don't think that this is your problem since the propagation speed is about 3.3 nanoseconds per metre - a small fraction of the clock period.

It would seem far more likely that you have signal "crosstalk" due to the capacitance between individual conductors of the ribbon cable.  If the clock and serial data signals are in adjacent conductors, the crosstalk may be reduced by having a grounded conductor interspersed between each of the signal leads.  Alternatively, you could utilize the lines used for other low frequency signals that already have bypass capacitance to ground.

If the MCU is the master, the simplest way to reduce the effect of signal distortion is to reduce the SPI clock frequency below the maximum allowable value - you might try a setting of say 1 MHz.

I do not like the idea of using 1nF shunt capacitors.  These may cause the outputs to become over-stressed, especially for high SPI clock frequencies.  If additional signal filtering is required, you might try fitting a series resistance at each output, say 100 - 300 ohms.  You would then use a much lower shunt capacitor value at the input pins, perhaps 30-100pF.  But this should be necessary only if lthe crosstalk reduction measures outlined above were not sufficient.

Regards,

Mac

[DSbob]

Hi Bigmac

I did say transmitting to '595s. Hard to make the MCU a slave with that on the other end!  I did not say I was transmitting at 20 MHz either.  That is the SMPS-PWM noise frequency (or possibly that noise ringing due to transmission line effects?).

In my previous attempts to address this issue, I had lowered the SPI frequency to 50 kHz!  Only need to send fast enough to multiplex two 7-segment digits in the driver subroutine, and very little processing between calls.

Crosstalk is certainly not my problem either.  I was alert enough to put the signals on alternate conductors and the signals are absolutely clean with an inactive SMPS.

I thank you for the last paragraph - had thought of adding or allowing for the series resistors although that is going to make a PCB spin quite tight.  However, from the above you can see high frequency SPI operation is not an issue.  I should probably look for a much worse case to experiment on, then try 0.1n.  Don't like the idea of some "exotic" intermediate value.

Bob

[DSbob · Accepted solution]

With help from Google, I found something that does not say "just don't do it!"

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN2434.pdf

From Freescale no less.  The capacitive loading section quantifies the effect on signal edges, but of course I knew that.

Still have not informed my SMPS vendor I can fix their problem.  I figure they deserve to find out why 2% of their product behaves so different from the rest.