Hello,
You do not say what ADC clock frequency you are using, and whether you have selected the long sampling interval? Let's assume so, and that you have an ADC clock of 1 MHz. The acquisition plus conversion period will be about 43 microseconds.
Where did you measure the waveform rise time? Between this point and the input pin, have you added any series resistance, or shunt capacitance? If so, the rise time may be considerably degraded.
Keep in mind that the required settling time will be many times the rise time to achieve a reading within 1 LSB at 10-bit resolution. For example, if the equivalent circuit is represented by a simple CR time constant, the settling time would need to be 7 times the time constant value. Measuring the rise time to 90 percent of the steady value, the settling period would need to be at least three times the measured rise time. With the equivalent of more than one CR time constant present, the settling time may need to be considerably longer, compared with the rise time.
Regards,
Mac