9S08QE8 - 6 lines of code runs in FLASH but not in RAM

[lazde]

Checking high FLASH registers in a 9S08QE8 works when code is executed in FALSH butcannot gain access to the registers when the same code is in RAM.  Anybody have any ideas?

Try these six lines of machine code in FLASH, then try it executed from RAM::

         ORG  ROMStart (for FLASH)  ORG RAMStart (for RAM)

         LDA   #$09

         STA  FCDIV

LP    LDA  FCDIV

         BPL  LP

LP2  JMP  LP2

I use CodeWarrior v6.3 and load the code into the QE8.  Run in FLASH and LP@ is were it ends up.  Run in RAM and the code loops at LP since it cannot read FCDIV from FLASH.  Is there something I should check?

[lazde]

I found the KEYACC bit must be set in the FCNFG register to enable access to the high page registers from code running in RAM.  With this bit not set, access to the high page FLASH registers in high page are denied and erroneous data is returned on a read.

[kef]

KEYACC should be set only for one purpose, to write backdoor unsecure key to NVBACKEYx locations as a part of backdoor unsecure procedure. While KEYACC is set, FLASH memory is not readable.

I don't know why FCDIV bit7 doesn't set while you are looping in RAM, maybe some read access to flash is required to made this bit set, I don't know. Try submitting service request for this here .

[lazde]

I agree the KEYACC bit should have nothing to do with this issue but it does resolve the reads from RAM.  I do have a service request on a related issue - when I attempt to erase a page of FLASH, the routine hangs waiting for confirmation the command has completed.  If KEYACC is set early in the code, the routine completes BUT does not erase FLASH. 

I am using the standard EraseFlash1, DoOnStack, and SpSub, BUSCLK at 2MHz, FCDIV at $09.  I get no access errors or protection violation errors and the routine JSR to FlashErase1 returns fine but does not erase FLASH. 

 Is there anything that must be set or cleared before calling the EraseFlash1 routine?

[lazde · Accepted solution]

The Reference Manual for the QE8 does not explain Bit 6,the FLS bit, in the System Clock gating Control 2 register (SCGC2).  It covers all the other bits but not the FLS bit.  If the FLS bit is set to 0, this will disable reading the FLASH high registers in $1820-$182B.  Once enabled, FLASH can be erased and reprogrammed in-application.