Hello,
My guess is that this may be occurring during a very slow ramp-up of the Vdd voltage, caused by external bulk capacitance. During this process, whilst the Vdd level is very low, and until the LVI hardware releases the reset condition, the I/O state is indeterminate. It may be possible that the I/O pin provides sufficient leakage current to turn on the transistor for a short period, prior to becoming an input immediately out of reset.
Depending on the load resistor at the collector of the PN100, the turn-on base current may be only a few microamps. To control the switching current level, a better solution may be to place an additional resistor between base and emitter of lthe transistor, say 10k. This will provide a threshold current level of 60-70 microamps.
Regards,
Mac
Addendum: I have just seen your second post.
After POR occurs, the pullup on IRQ pin is enabled by default. Again assuming a slow Vdd ramp-up, there may be a few milliseconds delay before the execution of insructions commences, after the LVI reset, for the second MCU, is released.