Assembly Commands on LPC812

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Assembly Commands on LPC812

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Rorrik on Mon Nov 17 11:42:21 MST 2014
I'm trying to jump my code to a new vector table location using the following code:

asm(".syntax unified");
asm("LDR.W SP, [R0]");
asm("LDR.W PC, [R0, #4]");
asm(".syntax divided");


On build I get the errors:

Error: selected processor does not support Thumb-2 mode `ldr.w SP,[R0]'
Error: selected processor does not support Thumb-2 mode `ldr.w PC,[R0,#4]'

Since the LPC812 does support some Thumb-2 commands, including LDR, I can't figure out how to fix this error. Is there something I need to include? Or is it a compiler setting? Is there a mode I need to set? Is there a different command that could serve the same purpose? I've tried STR with the same error.

Any help would be appreciated. Thanks!
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by MikeSimmonds on Mon Nov 17 13:30:09 MST 2014
What I said is not completely true.

You can 'mov' in and out of the high registers (effectively as tmp variables).
But most everything else add, sub, and, etc. etc. needs low registers.

But I assume that you don't need to go deep into M0 assembler.

If (when) you do, get hold of "Arm Architecture V7-M" pdf from infocenter.arm
And check the various instructions encodings for "All versions of the Thumb instruction set.".

And check out Joseph Yiu's book "The Definitive Guide to the ARM Cortex-M0" if you are that serious.

Mike.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Rorrik on Mon Nov 17 13:12:14 MST 2014
Thank you! Very helpful! This seems to be working great as far as I can see. Thank you for the explanation of why this needs to be done.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by MikeSimmonds on Mon Nov 17 12:33:31 MST 2014
Trying to use 'high' registers in the LDR is the problem specifically sp and pc.

You will have to go through an intermediate register or maybe two.

E.g
ldr r1, [r0]
mov sp, r1
ldr r1, [r0, 4]
bx r1 


or
ldr r1, [r0]
ldr r2, [r0, 4]
mov sp, r1
bx r2 


The M0 cannot use high registers (r8 to r15) except for sp (r13) and pc (r15) in very limited circumstances.

Mike

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