About SSI(I2S master mode problem),we used a chip pcm5100ADC on IMX6 solo board, it need I2S be master mode. It always failed. we found it seems have data without clk.

[huaiguangliu]

About I2S master mode problem,we used a chip pcm5100ADC on IMX6 solo board, it need I2S be master mo...

[zh597588308]

hi

     could you tell me your e-mail? I have the same question.

[saurabh206]

Hi

Please change SND_SOC_CLOCK_IN to SND_SOC_CLOCK_OUT.

snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_OUT);

You should get your playback.

Thanks

Saurabh

[huaiguangliu]

I have tried this but still failed. Now problem is here have any signal in BCK and LRCK. 

I can't see any init ssi_clk code in clock.c I doubt SSI module have no clock input,

I added some code in clock.c but it not work . Please see below  code. Did it right?

clk_set_parent(&ssi1_clk, &pll4_audio_main_clk);

    clk_enable(&pll4_audio_main_clk);

    rate = clk_round_rate(ssi1_clk, 12288000);

    clk_set_rate(&ssi1_clk,rate);

Thanks!

[saurabh206]

Have you changed the

static struct clk ssi1_clk

for correct .parent ?

[huaiguangliu]

No.I didn't.

Do you mean it will default use .parent?

It is strange when we play .wav , here hvae data siganl without any clk signal in ssi bus.

[saurabh206]

You need correct two things

snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_OUT);

and

static struct clk ssi1_clk = {

    __INIT_CLK_DEBUG(ssi1_clk)

    .parent = &pll4_audio_main_clk,

Please correct it and verify your audio.

Thanks

Saurabh

[huaiguangliu]

Do I need keep below code?

clk_set_parent(&ssi1_clk, &pll4_audio_main_clk);

    clk_enable(&pll4_audio_main_clk);

    rate = clk_round_rate(ssi1_clk, 12288000);

    clk_set_rate(&ssi1_clk,rate);

thanks!

[saurabh206]

yes

[huaiguangliu]

our bsp version is imx_kk4.4.2_1.0.0-ga

[huaiguangliu]

Today we found we use code imx6q_add_imx_ssi(1, &mx6_sabresd_ssi_pdata) that in fact we used ssi2, and we change code to below but still failed.

clk_set_parent(&ssi2_clk, &pll4_audio_main_clk);

    clk_enable(&pll4_audio_main_clk);

    rate = clk_round_rate(ssi2_clk, 12288000);

    clk_set_rate(&ssi2_clk,rate);

[liu_jialu]

have you solve the ssi2_clk problem? i meet the same problem, cat't get 12288000, but get 86016000 from /sys/kernel/debug/clock/osc_clk/pll4_audio_main_clk/ssi2_clk/rate

[Jacky_Song]

hi liu:

     i got same issue with SSI master mode. and i got no bclk or fsclk too. have you work out this problem?

[liu_jialu]

have you solve the ssi2_clk problem? i meet the same problem, cat't get 12288000, but get 86016000 from /sys/kernel/debug/clock/osc_clk/pll4_audio_main_clk/ssi2_clk/rate

[huaiguangliu]

unfortunnately, It still work failed.

DAC mclk is from clko(we can get and about is 24MHZ). and his parent is clko2_clk.

From datasheet we know we can set his parent is pll4_audio_main_clk. In this case. DAC mclk disappeared.

So can we doubt pll4_audio_main_clk have no clock?

Do we need set code clk_set_parent( &pll4_audio_main_clk,osc_clk)?

After I test it and still failed :smileysad:.

Correct：I make  a mistake, pll4_audio_main_clk have clk outout.Please ignore up  content..

Do you have any suggestions?

below is SSI register settings from trace when we start play .wav file.

tinyplay //data/PROmp15.wav -D 0

[Jenny DBG~~]imx_hifi_hw_params params_rate:44100[Jenny DBG~~]imx_ssi_set_dai_tdm_slot  SSI_STCCR = 0x40100

[Jenny DBG~~]imx_ssi_set_dai_fmt  SSI_STCR = 0x3ed scr=0x130

[Jenny DBG~~]snd_soc_dai_set_clkdiv cpu_dai done!!!

[Jenny DBG~~]imx_ssi_hw_paramschannels = 2 scr=0x1b8 SSI_STCCR = 0x4e104

Playing sample: 2 ch, 44100 hz, 16 bit

[Jenny DBG~~]imx_ssi_trigger  SSI_SCR = 0x1bb

[Jenny DBG~~]imx_ssi_trigger  SSI_SCR = 0x1b8

Thanks!

[huaiguangliu]

I doubt bsp didn't init ssi clock in clock.c of arch/arm/mach-mx6/

[saurabh206]

Hi Liu

Which BSP and kernel you are using?

What modification do you have made?

Default BSP doesn't support SSI master.

Thanks

Saurabh

[huaiguangliu]

kernel 3.0.35,mach-mx6,board-mx6q-sabresd.

[huaiguangliu]

We follow datasheet <i.MX 6Solo/6DualLite Applications Processor Reference Manual>  SSI I2S master mode to set SSI reg. .  In pcm51xx dai driver call cpu_dai to set format and clk.

[saurabh206]

Hi

Have you changed platform driver from "SND_SOC_DAIFMT_CBM_CFM" to "SND_SOC_DAIFMT_CBS_CFS"?

Have you set MCLK and SSI clock?

[huaiguangliu]

We have set and can get MCLK in pcm5100 DAC.

in pin DIN and SCK we can get signal ,BCk and LRCK have nothing.

Please see our settings:

dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |

        SND_SOC_DAIFMT_CBS_CFS;

    ssi_mode->flags |= IMX_SSI_SYN;

    /* set cpu DAI configuration */

    ret = snd_soc_dai_set_fmt(cpu_dai, dai_format);

    if (ret < 0){

        pr_err("hw_params snd_soc_dai_set_fmt cpu_dai failed : %d\n", ret);

        return ret;

    }

    /* set the SSI system clock as input (unused) */

    snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_IN);

    snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 4);

    snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, 1);

    snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, 0);