Functionality is described, but it is not clear for me how it works for 16 bit access. In the figure 23-7 which bit is the lsb of address? A31? How does it look like for x8 memory? Will the shift be only 4 bits and A27 will be involved?
On the figure 23-12, I think 2nd row should be shifted right 1 bit, which makes the word address (i.e. the 'x' is missing in the bit0). The real confusion comes with figure 23-16, where the AD0 signal should contain the A0 bit of address (as per 23-17), but in the 23-16 at AD0 bit position, the bit 30 is shown.
And now for booting - I have an option for 4 bit shift only in the cfg_rcw_src[6:7].Will this work or I am unable to boot in ADM MODE 1 from 16 bit parallel flash?