IMX7 SDIO detail HW guideline for layout?

[frankyhsu]

We are doing the layout but we found the SDIO layout is not detail in HW design guide including the maximum length allowed and the tolerance. It should be described in detail in the HW design guide. Could you please help to have some comment for this?

Thanks.

Franky.

[frankyhsu]

Hi Igor,

Got it. As you said, it will be case by case.

Thanks.

[igorpadykov]

Hi Franky

one can follow sect.3.5.8 High speed signal routing recommendations i.MX6 System
Development User’s Guide
http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards
igor
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[frankyhsu]

Hi Igor,

The document is good for us and it includes most suggestion but we are still lack of information about the maximum SDIO allowed length and tolerance. The tolerance can be found on a HW review checking excel with a +/-50mil requirement. The maximum length become the only question we are highlighted by my customer. We use eMMC and WiFi module on SDIO bus.

Thanks.

[igorpadykov]

Hi Franky

document recommends :

Similar DDR rules must be followed for data, address and control as for SD module interfaces.

~igor

[frankyhsu]

Hi Igor,

The DDR length defined in "IMX7DSHDG" guideline shows maximum is 1400mils for LPDDR2/3 and 1900mils for DDR3. Both 1400mil and 1900mil is small for a system application. The i.MX7 Sabre EVB also has more than 3000mil SDIO trace. That's why we do not think the value defined for DDR can not be used on SDIO case that the EVB seems also to violate it.

Thanks.

[igorpadykov · Accepted solution]

Hi Franky

one can use ibis simulations, I am not aware of special SDIO trace length restrictions.

~igor