Hi Jeffrey,
in one of the generated files Cpu.c there is something very strange. See the code snippet below on the line (09).
#if CPU_COMPONENTS_INIT
void Components_Init(void)
{
/*! uartCom1 Auto initialization start */
OSA_InstallIntHandler(UART1_RX_TX_IRQn, UART1_MSJ_IRQHandler);
UART_DRV_Init(FSL_UARTCOM1,&uartCom1_State,&uartCom1_InitConfig0);
UART_DRV_InstallRxCallback(FSL_UARTCOM1, uartCom1_RxCallback, uartCom1RxBuff, NULL, true);
NVIC_SetPriority(UART1_RX_TX_IRQn, 80U);
/*! uartCom1 with DMA Auto initialization end */
/*! gpio1 Auto initialization start */
GPIO_DRV_Init(NULL,gpio1_OutConfig0);
/*! gpio1 Auto initialization end */
}
#endif /* CPU_COMPONENTS_INIT */
The second argument passed to NVIC_SetPriority is 80U which is very strange. When we look into core_cm4.h implementation, we will see the value is left shifted by some number of bits (I guess by 4 on Kinetis as it has 4 interrupt priority bits) and then there is binary AND with 0xff and finally the result is written into an array of uint8_t in NVIC->IP[]. So I'm afraid this operation actually produces zero that is written to NVIC priority. This is actually above the MQX critical section priority (when MQX enters critical section it masks interrupts priority level 2 and lower, so an isr with zero priority can interrupt MQX critical section).
Now if you're using blocking UART_DRV methods to receive data, the UART_DRV interrupt routine would call semaphore api inside (post rx semaphore when all requested chars have been received).
This can corrupt MQX scheduler context I'm afraid, as the semaphore post migth be called inside MQX critical section.
By making the long story short, I'd recommend to try with something like NVIC_SetPriority(UART1_RX_TX_IRQn, 6); (use even priority level lower than 2).
Martin