imx6q sabre AI board MIPI camera.

[GaoJianzhong]

Hi all,

I am trying to write a custom mipi camera module connect to imx6q sabre auto board.

The custom camera's details is as bellow:

4 data lanes,

YUV422 8 bit data format,

And it is no need to send any control command to camera module(it will work when power on)

And I referenc the ov5640_mipi camera driver, and delete the source code about I2C control.

Now, the problem is that when i excute the /unit_tests/mxc_v4l2_capture.out as follow:

./mxc_v4l2_capture.out -d /dev/video1

I got the errors message:

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

VIDIOC_DQBUF failed.

ERROR: v4l2 capture: VIDIOC_QBUF: buffer already queued

And I got the MIPI registers value:

0x021DC000:  3130302A 00000003 00000001 00000001

0x021DC010:  00000001 000002F0 00000000 00000000

0x021DC020:  00000000 00000000 00000000 00000000

0x021DC030:  00000000 00001414 00000000 00000000

I found that ov5640 camera on sabre sd board, the values are:

0x021DC000:  3130302A 00000001 00000001 00000001

0x021DC010:  00000001 00000330 00000000 00000000

0x021DC020:  00000000 00000000 00000000 00000000

0x021DC030:  00000000 00001414 00000000 00000000

The address 0x021DC014 register's bit 8 is different. (this bit Indicates that the clock lane is actively receiving a DDR clock)

I am not clearly with MIPI

Is there any ideas to help me go on?

Thank you very much.

[meflo]

Hi everybody,

am having a similar problem described in this thread.

I am trying to capture some data from a decoder connected to an imx6 quad board through 1 data lane connection.

The connection is through IPU 0, CSI 1.

The relevant structures are:

static struct fsl_mxc_camera_platform_data mipi_csi2_data = {

       .mclk = 108000000,

       .mclk_source = 0,

       .csi = 1,

       .io_init = mx6q_dec_init,

       .pwdn = NULL,

};

static struct mipi_csi2_platform_data mipi_csi2_pdata = {

       .ipu_id      = 0,

       .csi_id      = 1,

       .v_channel      = 1,

       .lanes             = 1,

       .init                = mx6q_dec_init,

       .dphy_clk        = "mipi_pllref_clk",

       .pixel_clk        = "emi_clk",

};

static struct fsl_mxc_capture_platform_data capture_data[] = {

     {

          .csi = 1,

          .ipu = 1,

          .mclk_source = 0,

          .is_mipi = 0,

          },

          {

          .csi = 1,

          .ipu = 0,

          .mclk_source = 0,

          .is_mipi = 1,

          },

};

The problem I am having is:

MIPI_CSI_PHY_STATE register has the value 0x210 ; so the phy_rxclkactivehs is always 0.

The clock that is output from the decoder to the imx module is 108 MHz. I found references in this forum stating that: the MIPI DPHY clock should match the camera sensor clock.

So, I should be setting the CSI2_PHY_TST_CTRL1 register like:

mipi_csi2_write(info, 0x00000040, CSI2_PHY_TST_CTRL1);

But still the phy_rxclkactivehs bit is never set.

Also, from within the driver, trying to use the set_mclk_rate() function, I can see using debug that it enters the function with the desired value, 108000000 but when it exist it actually just sets it at 24000000.

Any ideas?

Thank you

[wallyyeh]

Hi, Meton:

   I'm facing same problem, phy_rxclkactivehs never set as 1, and set_mclk_rate() always keep 24000000.

do you have solved this issue?

Thanks

[aliismail]

Hi Wally,

Did you by chance ever figure out what solved this issue?

Thanks!

[wallyyeh]

Hi, Ali:

    yes, please refer my thread:

A Simple tutor for writing i.MX6 mipi driver, use adv7480 as an example 

here's my solution:

some important part：

1. adv7480_init_mode(), I found after mipi_csi2_reset_with_dphy_freq() or mipi_csi2_reset() called, you *must* turn off device's output and turn it on again! or you will got mipi_csi2_dphy_status alwaly be 0x200 or 0x230, it means i.MX6 can't get the clock form device.

[aden]

Hi, gao

I've encountered same problem which you described in top of question.

We have a FPGA mipi interface on CSI1 of IPU0, using 4 lanes

When I initialized the MIPI PHY, the status register was 6F0--> 200 --> 600 --> 200.

As above, MIPI_CSI_PHY_STATE bit 8 (phy_rxclkactivehs) is never setted.

What cause this symptom? If you have any idea please help me..

[linyang1]

hi,gao, i am also play the ov5640_mipi on imx6q sabresd , and my board configure file is mach-mx6/board-mx6q_sabresd.c .

but i don't know how to set MIPI_CSI_PHY_STATE ,

i do it :

drivers/media/video/mxc/capture/ov5640_mipi.c

if (mipi_csi2_info) {

                unsigned int i;

                i = 0;

                /* wait for mipi sensor ready */

                mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);

                printk("ov5640-----mipi_reg 0 : 0x%x \n", mipi_reg);                  // ********* i print it here

                while ((mipi_reg == 0x200) && (i < 10)){

                         mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);

                        i++;

                        msleep(10);

                }

my mipi_reg is  0x10 and  0x0 . and i am not sure is it read here right?

can you help me?

[joštnovak]

Hello,

i have similar problem regarding camera as well. I am using 2 lane MIPI interface and driver similar to ov5640_mipi.

When i execute "./mxc_v4l2_capture.out -d /dev/video1 -m 1" i get following errors:

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

VIDIOC_DQBUF failed.

ERROR: v4l2 capture: VIDIOC_QBUF: buffer already queued

VIDIOC_QBUF failed

During program execution MIPI  registers take following values:

0x021DC000:  3130302A 00000001 00000001 00000001

0x021DC010:  00000001 00000200 00000000 00000000

0x021DC020:  00000000 00000003 00000000 00000000

0x021DC030:  00000000 00001414 00000000 00000000

a.) Register 0x21DC024 indicates errors. Bit 0 and bit 1 are set:

Escape Entry Error (ULPM) on data lane 0

Escape Entry Error (ULPM) on data lane 1

I can't figure out, what does this error mean, or how to fix it.

b.) Register 0x021DC014 bits 4,5 (Data lane 0,1 in Stop state) continuously change value during execution, which does not make sense to me.

Any information would really help me!

Regards,

Novak Jost

[GaoJianzhong]

Hi

1.  You must initilize the mipi module before start the camera clock lane signal.

     Please confirm this.

2.  MIPI_CSI_ERR2 register has errors may mean that you should change the MIPI_CSI_PHY_TST_CRTL0 values, this is not documented in RM.

[joštnovak]

Hy, thank you for fast repond!

MIPI module is initialized and i got rid of errors in MIPI_CSI_ERR2 register.

Now i got to similar problem as stated in your original post:

MIPI register values:

0x021DC000:  3130302A 00000001 00000001 00000001

0x021DC010:  00000001 00000230 00000000 00000000

0x021DC020:  00000000 00000000 00000000 00000000

0x021DC030:  00000000 00001414 00000000 00000000

MIPI registers when using ov5640 camera:

0x021DC000:  3130302A 00000001 00000001 00000001

0x021DC010:  00000001 00000330 00000000 00000000

0x021DC020:  00000000 00000000 00000000 00000000

0x021DC030:  00000000 00001414 00000000 00000000

Did you solve your problem entirely by changing virtual channel or did you take any other actions.

I would appreciate any other thoughts as well.

Regards

Novak Jost

[GaoJianzhong]

Hi

As i said in last message.

You must initialize the i.mx6’s MIPI module firstly,

And then turn on the camera to output the mipi signal.

If you initialize the MIPI module when camera is already outputting the signal,

the clock lane will not work.

This is no matter with the virtual channel.

Your must get the clock lane work(0x021DC014=0x00000330), and then debug the virtual channel.

[hyunjaejun]

I attaching a 8bit Raw 8mega 2lane 15frame MIPI Camera.

also, i use MIPI CAMERA at same port on SDP board.

----------------------------------------------------------------------------------------------------------------------------------------------------------------

See my Log.

[ ov5640_mipi.c in Kernel ] ov5640_init_mode In, ov5640_mode_INIT

[ ov5640_mipi.c in Kernel ] ov5640_set_virtual_channel In, set_virtual_channel : 1

[ ov5640_mipi.c in Kernel ] 1. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

[ ov5640_mipi.c in Kernel ] 2. >>>>>> mipi_status_reg : 0x200

mipi csi2 can not receive sensor clk!

[ ov5640_mipi.c in Kernel ] ov5640_init_mode In, mode_direct

[ ov5640_mipi.c in Kernel ] ov5640_change_mode_direct In

[ ov5640_mipi.c in Kernel ] ov5640_set_virtual_channel In, set_virtual_channel : 1

[ ov5640_mipi.c in Kernel ] 1. >>>>>> mipi_status_reg : 0x300

[ ov5640_mipi.c in Kernel ] 1. >>>>>> mipi_error_reg : 0

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

VIDIOC_DQBUF failed.

----------------------------------------------------------------------------------------------------------------------------------------------------------------

In last month, i attached IR 8/10 bit Raw parallel camera.

At that time, i used Generic Data type.

for this time, i used Generic Data type.

i confirmed CLKM/P, DAT0P/M, DATA1P/M for OSC.

but, i can't received a data.

In Debug steps for customer MIPI sensor,

The range and the exact value when ref_clock is 27M are showed as below:

#define PLL_CLK  0x32  //783Mhz

// clock_range : register value // exact value when ref clock is 27M

                   // 950-1000MHz :0x74   //999Mhz

//  900-950Mhz  :0x54   //972Mhz

//  800-850MHz  :0x14   //849Mhz

mipi_csi2_write(info, 0x00000014, CSI2_PHY_TST_CTRL1);  // ov5640 output clk.

My camera operate in 24Mhz of Mclk and 648Mhz of PLL_freq.

what's the my setting value?     mipi_csi2_write(info, ??????? , CSI2_PHY_TST_CTRL1);

[wsh1001]

I use IMX6q as master cpu.

I have changed the driver ov5640_camera_mipi.c to adjust my camera IMx132, in linux 3.0.35.

The i2c write and read is ok, but after i send the i2c data to change the register of the Imx132 sensor and let it go,

the IMX6 can not receive the clk from sensor.

It tells me mipi csi2 can not receive sensor clk!

The register  MIPI_CSI_PHY_STATE is always 0x200!

MIPI_CSI_ERR1，MIPI_CSI_ERR2 is all 0x0.

I've change the lanes number to 1.

I've read the document Debug steps for customer MIPI sensor.

The sensor's input clk is 24Mhz, the differential clk  is 810Mhz.

I've looked through the mxc_mipi_csi2.c, the command

mipi_csi2_write(info, 0x00000014, CSI2_PHY_TST_CTRL1); is also fit my design in my point.

And also i patch linux 3.0.35 , when the hdmi clk is not used, i could have the mclk 24Mhz.

also i've tried the linux 3.10.17, which has patched the hdmi clk problem officially.

After i've tried the above, the problem is also unfixed. I don't know the reason.

Who can tell me what else should I try?

[joštnovak]

Hey,

I managed to get it working! :smileyhappy:

After fixing MIPI initialization (as you said), i had to configure virtual channel and IPU registers, then first pictures appeared.. Still wrong format and colorspace, but it's a big step towards my goal.

Thank you again, i really appreciate your help!

Regards,

Novak Jost

[meflo]

Hi,

what fixes did you do for this? How was your MIPI initialisation done?

Thanks

[sathyakumarselv]

Hi Novak,

I was also facing the same issue.

As per Gao Jianzhong reply, error on MIPI lane was solved.

MIPI_CSI_ERR2 register has errors may mean that you should change the MIPI_CSI_PHY_TST_CRTL0 values, this is not documented in RM.

But reconstructing the image with proper format is getting missed somewhere. Have you solved this issue? I have verified configuration on sensor, MIPI gasket, CSI and SMFC. But everything was configured correctly, even then UYVY sensor information is received at DMA as YUYV. Any idea on solving this issue?

Regards,

Sathya Kumar P

[joštnovak]

Hi Sathya,

maybe wrong format settings for CPMEM? IPU_CSI sensor data format register is not important if you are using CSI->MEM path.

I am working with bayer format and not UYVY format, so i am not sure how to assist you.

Sorry for late respond and i hope you all ready found solution.

Regards.

[sathyakumarselv]

Hi Novak,

Platform configuration were correct, but there was some inconsistent I2C failure happened while writing format related sensor registers. After fixing those issue, now everything works great:-)

Thank you.

Sathya Kumar P

[GaoJianzhong]

Hi all,

I have got this mipi camera worked.

The reason is camera use virtual channel 0,  it only goes to CSI0 of IPU1.

But my driver is reference the sabreSD board, it use CSI1 of IPU1.

Now my driver can get the 1280x720 picture, but not 2560x1440.

I think the problem is in IPU, it seems that there is a bus neck on IPU block.

Does 2560x1440@30fps camera over the i.mx6q support?

Is there anyone  know about this?

Thank you.

[GaoJianzhong · Accepted solution]

I have got this worked.

whe  i set the AXI_CLK_ROOT clock to 528Mhz,(default 264Mhz),

2560x1440@30fps is worked fine.

So it seems that the "ccm_pixel_clk" is not enough in CSI2IPU moudle or MIPI core.

Is there anyone know where can i get detail information about this in freescale documents.

Than kyou.

[aravinthkumarja]

Hi Gao Jianzhong ,

How to configure AXI_CLK_ROOT.

i tried in board file, i can't do.