The patch flips the polarity of the PWM and inverts the input setting.
So the PWM glitches LOW instead of glitching HIGH.
But it still glitches!
Isn't this a silicon bug? Shouldn't there be an Errata Item with "setting the REPEAT bits" being listed as a Workaround?
I've just had this happen to me, and have reported it here with an oscilloscope trace showing the problem:
i.MX53 (possibly i.MX6) PWM Glitches on Duty Cycle Change
The Reference Manuals state:
51.7.5 PWM Sample Register (PWMx_PWMSAR) (52.7.5 in i.MX6SDL manual)
The PWM will run at the last set duty-cycle setting if all the (52.75 in i.MX6 values of
the FIFO has been utilized, until the FIFO is reloaded or the PWM is disabled. When a
new value is written, the duty cycle changes after the current period is over.
The above isn't happening. It only seems to be true if a new value is written while the FIFO isn't empty. When the FIFO is empty the PWM acts on the new value immediately.
I've got a fix that involves reading PWMSAR, writing that to PWMSAR (to load up the FIFO) and then write the NEW value into PWMSAR. That also synchronises the duty cycle to the end of the current period.
It is interesting that setting the REPEAT bits also seems to fix this.
Tom